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1. 发明授权

US08700840B2 Nonvolatile memory with write cache having flush/eviction methods 有权
标题翻译：具有写入缓存的非易失性存储器具有刷新/驱逐方法
公开(公告)号：US08700840B2
公开(公告)日：2014-04-15
申请号：US12348895
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/08 , G11C11/34
CPC分类号： G06F12/0866 , G06F12/0246 , G06F12/0804 , G06F2212/7203 , G06F2212/7204 , G11C11/5628 , G11C2211/5641 , Y02D10/13
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。将数据从高速缓冲存储器归档到主存储器的决定取决于要归档的数据的属性，主存储器部分中的块的状态和高速缓存部分中的块的状态。

2. 发明授权

US08244960B2 Non-volatile memory and method with write cache partition management methods 有权
标题翻译：非易失性存储器和写入缓存分区管理方法
公开(公告)号：US08244960B2
公开(公告)日：2012-08-14
申请号：US12348899
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/224 , G06F2212/7203 , G06F2212/7204
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。优选地，分配耐力计数高于平均值的块。数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。

3. 发明申请

US20100174847A1 Non-Volatile Memory and Method With Write Cache Partition Management Methods 有权
标题翻译：非易失性存储器和写缓存分区管理方法
公开(公告)号：US20100174847A1
公开(公告)日：2010-07-08
申请号：US12348899
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0866 , G06F2212/224 , G06F2212/7203 , G06F2212/7204
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。响应于增加容量的需求，高速缓冲存储器具有通过从主存储器分配块而动态增加的容量。优选地，分配耐力计数高于平均值的块。数据的逻辑地址被划分为区域以限制高速缓存的索引的大小。

4. 发明授权

US08094500B2 Non-volatile memory and method with write cache partitioning 有权
标题翻译：非易失性存储器和写缓存分区的方法
公开(公告)号：US08094500B2
公开(公告)日：2012-01-10
申请号：US12348891
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C16/0483 , G11C29/00 , G11C29/76 , G11C29/808 , G11C2211/5641 , G11C2211/5643
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。将数据写入高速缓冲存储器或直接写入主存储器的决定取决于要写入的数据的属性和特性，主存储器部分中的块的状态和高速缓存部分中块的状态。

5. 发明申请

US20100174846A1 Nonvolatile Memory With Write Cache Having Flush/Eviction Methods 有权
标题翻译：具有缓冲/驱逐方法的写缓存的非易失性存储器
公开(公告)号：US20100174846A1
公开(公告)日：2010-07-08
申请号：US12348895
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G06F12/02 , G06F12/00 , G06F12/08
CPC分类号： G06F12/0866 , G06F12/0246 , G06F12/0804 , G06F2212/7203 , G06F2212/7204 , G11C11/5628 , G11C2211/5641 , Y02D10/13
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to archive data from the cache memory to the main memory depend on the attributes of the data to be archived, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。将数据从高速缓冲存储器归档到主存储器的决定取决于要归档的数据的属性，主存储器部分中的块的状态和高速缓存部分中的块的状态。

6. 发明申请

US20100172180A1 Non-Volatile Memory and Method With Write Cache Partitioning 有权
标题翻译：非易失性存储器和使用写高速缓存分区的方法
公开(公告)号：US20100172180A1
公开(公告)日：2010-07-08
申请号：US12348891
申请日：2009-01-05
申请人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
发明人： Alexander Paley , Sergey Anatolievich Gorobets , Eugene Zilberman , Alan David Bennett , Shai Traister , Andrew Tomlin , William S. Wu , Bum Suck So
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C16/0483 , G11C29/00 , G11C29/76 , G11C29/808 , G11C2211/5641 , G11C2211/5643
摘要： A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.
摘要翻译：将非易失性存储器的一部分从主多层存储器阵列分区以作为高速缓存进行操作。缓存存储器被配置为以比每个存储器单元更少的容量存储和与主存储器相比写入单元的更细粒度。在面向块的存储器架构中，缓存具有多个功能，而不仅仅是提高访问速度，而是顺序更新块系统的组成部分。将数据写入高速缓冲存储器或直接写入主存储器的决定取决于要写入的数据的属性和特性，主存储器部分中的块的状态和高速缓存部分中块的状态。

7. 发明授权

US08250333B2 Mapping address table maintenance in a memory device 有权
标题翻译：映射存储设备中的地址表维护
公开(公告)号：US08250333B2
公开(公告)日：2012-08-21
申请号：US12348782
申请日：2009-01-05
申请人： Sergey Anatolievich Gorobets , Alexander Paley , Eugene Zilberman , Alan David Bennett , Shai Traister
发明人： Sergey Anatolievich Gorobets , Alexander Paley , Eugene Zilberman , Alan David Bennett , Shai Traister
IPC分类号： G06F12/12
CPC分类号： G06F12/0246 , G06F12/1027 , G06F2212/1016 , G06F2212/7201 , G06F2212/7205
摘要： A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.
摘要翻译：方法和系统维护用于将逻辑组映射到存储器设备中的物理地址的地址表。该方法包括接收在地址表中设置条目的请求，并根据高速缓存中的条目的存在以及高速缓存是否满足冲洗阈值标准来选择和刷新地址表高速缓存中的条目。刷新的条目包括小于地址表缓存的最大容量。刷新阈值标准包括地址表缓存是否满或页面是否超过已更改条目的阈值。地址表和/或地址表缓存可以存储在非易失性存储器和/或随机存取存储器中。由于将地址表缓存部分刷新到地址表所需的写入操作次数和时间减少，因此可能会导致使用此方法和系统的性能提高。

8. 发明申请

US20100174869A1 MAPPING ADDRESS TABLE MAINTENANCE IN A MEMORY DEVICE 有权
标题翻译：映射地址表维护存储器件
公开(公告)号：US20100174869A1
公开(公告)日：2010-07-08
申请号：US12348782
申请日：2009-01-05
申请人： Sergey Anatolievich Gorobets , Alexander Paley , Eugene Zilberman , Alan David Bennett , Shai Traister
发明人： Sergey Anatolievich Gorobets , Alexander Paley , Eugene Zilberman , Alan David Bennett , Shai Traister
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F12/1027 , G06F2212/1016 , G06F2212/7201 , G06F2212/7205
摘要： A method and system maintains an address table for mapping logical groups to physical addresses in a memory device. The method includes receiving a request to set an entry in the address table and selecting and flushing entries in an address table cache depending on the existence of the entry in the cache and whether the cache meets a flushing threshold criteria. The flushed entries include less than the maximum capacity of the address table cache. The flushing threshold criteria includes whether the address table cache is full or if a page exceeds a threshold of changed entries. The address table and/or the address table cache may be stored in a non-volatile memory and/or a random access memory. Improved performance may result using this method and system due to the reduced number of write operations and time needed to partially flush the address table cache to the address table.
摘要翻译：方法和系统维护用于将逻辑组映射到存储器设备中的物理地址的地址表。该方法包括接收在地址表中设置条目的请求，并根据高速缓存中的条目的存在以及高速缓存是否满足冲洗阈值标准来选择和刷新地址表高速缓存中的条目。刷新的条目包括小于地址表缓存的最大容量。刷新阈值标准包括地址表缓存是否满或页面是否超过已更改条目的阈值。地址表和/或地址表缓存可以存储在非易失性存储器和/或随机存取存储器中。由于将地址表缓存部分刷新到地址表所需的写入操作次数和时间减少，因此可能会导致使用此方法和系统的性能提高。

9. 发明授权

US08452911B2 Synchronized maintenance operations in a multi-bank storage system 有权
标题翻译：在多银行存储系统中进行同步维护操作
公开(公告)号：US08452911B2
公开(公告)日：2013-05-28
申请号：US12895383
申请日：2010-09-30
申请人： Sergey Anatolievich Gorobets , Alan David Bennett , Charles Michael Schroter , Eugene Zilberman
发明人： Sergey Anatolievich Gorobets , Alan David Bennett , Charles Michael Schroter , Eugene Zilberman
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above.
摘要翻译：公开了一种用于管理多库非易失性存储装置中的维护操作的方法和系统。该方法包括从主机系统接收数据写入命令和相关联的数据以存储在非易失性存储设备中，并将数据写入命令的头部指向数据写入命令的尾部中的第一个存储体，其中数据写入命令的头部仅包括具有在数据写入命令的尾部中的数据的逻辑块地址之前的逻辑块地址的数据。当第一行的状态延迟数据写入命令的执行时，控制器执行第二存储体中的第二存储体维护过程，同时指向第一和第二存储体的数据写入命令正在等待。该系统包括多个银行，其中每个银行可以与相同或不同的控制器相关联，并且一个或多个控制器适于执行上述方法。

10. 发明申请

US20120084489A1 SYNCHRONIZED MAINTENANCE OPERATIONS IN A MULTI-BANK STORAGE SYSTEM 有权
标题翻译：多银行存储系统中的同步维护操作
公开(公告)号：US20120084489A1
公开(公告)日：2012-04-05
申请号：US12895383
申请日：2010-09-30
申请人： Sergey Anatolievich Gorobets , Alan David Bennett , Charles Michael Schroter , Eugene Zilberman
发明人： Sergey Anatolievich Gorobets , Alan David Bennett , Charles Michael Schroter , Eugene Zilberman
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7205
摘要： A method and system for managing maintenance operations in a multi-bank non-volatile storage device is disclosed. The method includes receiving a data write command and associated data from a host system for storage in the non-volatile storage device and directing a head of the data write command to a first bank in the and a tail of the data write command to a second bank, where the head of the data write command only includes data having logical block addresses preceding logical block addresses of data in the tail of the data write command. When a status of the first bank delays execution of the data write command the controller executes a second bank maintenance procedure in the second bank while the data write command directed to the first and second banks is pending. The system includes a plurality of banks, where each bank may be associated with the same or different controllers, and the one or more controllers are adapted to execute the method noted above.
摘要翻译：公开了一种用于管理多库非易失性存储装置中的维护操作的方法和系统。该方法包括从主机系统接收数据写入命令和相关联的数据以存储在非易失性存储设备中，并将数据写入命令的头指向数据写入命令的尾部中的第一个存储体，其中数据写入命令的头部仅包括具有在数据写入命令的尾部中的数据的逻辑块地址之前的逻辑块地址的数据。当第一行的状态延迟数据写入命令的执行时，控制器执行第二存储体中的第二存储体维护过程，同时指向第一和第二存储体的数据写入命令正在等待。该系统包括多个银行，其中每个银行可以与相同或不同的控制器相关联，并且一个或多个控制器适于执行上述方法。

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