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1. 发明授权

US06686250B1 Method of forming self-aligned bipolar transistor 失效
标题翻译：形成自对准双极晶体管的方法
公开(公告)号：US06686250B1
公开(公告)日：2004-02-03
申请号：US10300105
申请日：2002-11-20
申请人： Alexander Kalnitsky , Michael Rowlandson , Fanling H. Yang , Sang Park , Robert F. Scheer
发明人： Alexander Kalnitsky , Michael Rowlandson , Fanling H. Yang , Sang Park , Robert F. Scheer
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has an emitter region characterized by a y-shaped structure formed from bilayer polysilicon. The bilayer polysilicon includes a first polysilicon emitter structure and a second polysilicon emitter structure. The method of forming the bipolar transistor includes forming an emitter stack on a substrate. The emitter stack comprises the first polysilicon emitter structure and a plug structure. The emitter stack defines the substrate into a masked portion and exposed adjacent portions. The exposed adjacent portions are selectively doped with a dopant to define an extrinsic base region, wherein the dopant is blocked from entering the masked portion. After selectively doping the extrinsic base region, the plug structure is removed from the emitter stack and the second polysilicon emitter structure is formed on the first polysilicon emitter structure to define the emitter region of the bipolar transistor.
摘要翻译：提供自对准双极晶体管及其形成方法。双极晶体管具有由双层多晶硅形成的由y形结构表征的发射极区域。双层多晶硅包括第一多晶硅发射极结构和第二多晶硅发射极结构。形成双极晶体管的方法包括在衬底上形成发射极叠层。发射极堆叠包括第一多晶硅发射极结构和插塞结构。发射极堆叠将衬底限定为掩模部分并暴露于相邻部分。暴露的相邻部分被选择性掺杂掺杂剂以限定非本征基区，其中掺杂剂被阻止进入掩蔽部分。在选择性地掺杂非本征基极区域之后，将插塞结构从发射极堆叠移除，并且第二多晶硅发射极结构形成在第一多晶硅发射极结构上以限定双极晶体管的发射极区域。

2. 发明授权

US07026666B2 Self-aligned NPN transistor with raised extrinsic base 有权
公开(公告)号：US07026666B2
公开(公告)日：2006-04-11
申请号：US10734928
申请日：2003-12-12
申请人： Alexander Kalnitsky , Alexel Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
发明人： Alexander Kalnitsky , Alexel Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
IPC分类号： H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/1004 , H01L29/7378
摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

3. 发明授权

US06767798B2 Method of forming self-aligned NPN transistor with raised extrinsic base 有权
标题翻译：形成具有凸起外在基极的自对准NPN晶体管的方法
公开(公告)号：US06767798B2
公开(公告)日：2004-07-27
申请号：US10119594
申请日：2002-04-09
申请人： Alexander Kalnitsky , Alexei Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
发明人： Alexander Kalnitsky , Alexei Shatalov , Michael Rowlandson , Sang H. Park , Robert F. Scheer , Fanling H. Yang
IPC分类号： H01L21331
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/1004 , H01L29/7378
摘要： A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.
摘要翻译：提供自对准双极晶体管及其形成方法。双极晶体管具有凸起的外在基极，使得通过提供比本征基底更厚的外在基极来降低连接基极电阻。外部基极的厚度的增加提供了重掺杂基极区域的较小电阻层。形成双极晶体管的方法包括在衬底上沉积第一外延层以形成具有本征基极区域和非本征基极区域的基极区域。通过在第一外延层的一部分上沉积第二外延层使外部基极层的厚度为x，并且本征层的厚度为y，其中x> y，凸起外部基极区域。使用化学气相外延装置沉积第二外延层，其中Ge至Si的浓度在外延过程中从高于5％逐渐降低至接近0％。因此，第二外延层在第一和第二外延层的界面附近具有最高的Ge浓度。在第二外延区域的顶面，Ge的浓度逐渐降低到接近0％。

4. 发明授权

US06861324B2 Method of forming a super self-aligned hetero-junction bipolar transistor 有权
标题翻译：形成超自对准异质结双极晶体管的方法
公开(公告)号：US06861324B2
公开(公告)日：2005-03-01
申请号：US09882538
申请日：2001-06-15
申请人： Alexander Kalnitsky , Michael Rowlandson , Ken Liao , Robert F. Scheer
发明人： Alexander Kalnitsky , Michael Rowlandson , Ken Liao , Robert F. Scheer
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L29/7378
摘要： The present invention provides a method of forming a super self-aligned bipolar transistor with enhanced electrical characteristics. The power gain and frequency response of the transistor are improved by horizontally etching an area for the base region that is wider than the active emitter and collector regions. By removing polysilicon layers within the device, the base region resistance goes down and unwanted capacitive effects are reduced.
摘要翻译：本发明提供一种形成具有增强的电特性的超自对准双极晶体管的方法。通过水平蚀刻比有源发射极和集电极区域宽的基极区域的区域来提高晶体管的功率增益和频率响应。通过去除器件内的多晶硅层，基极区电阻下降，不必要的电容效应降低。

5. 发明授权

US06845044B2 Method of preventing high Icc at start-up in zero-power EEPROM cells for PLD applications 失效
标题翻译：用于PLD应用的零功率EEPROM单元启动时防止高Icc的方法
公开(公告)号：US06845044B2
公开(公告)日：2005-01-18
申请号：US10061057
申请日：2002-01-29
申请人： Andrew Horch , Michael Rowlandson
发明人： Andrew Horch , Michael Rowlandson
IPC分类号： H01L27/115 , G11C16/04
CPC分类号： H01L27/115
摘要： A CMOS memory cell (FIG. 1) is provided which includes a PMOS transistor (102) and an NMOS transistor (104) with a common floating gate and common drains configured to prevent a large drain of Icc current from a power supply during power-up. To prevent the large Icc during power-up, the threshold voltages of the PMOS transistor (102) and NMOS transistor (104) are set so that the PMOS transistor (102) and NMOS transistor (104) do not turn on together, irrespective of charge initially stored on the floating gate. Without such thresholds, a significant drain of current Icc from the power supply connection Vcc can occur since charge initially on the floating gate leaves both the PMOS transistor (102) and the NMOS transistor (104) on creating a path for Icc from Vcc to Vss.
摘要翻译：提供了一种CMOS存储器单元（图1），其包括具有公共浮置栅极的PMOS晶体管（102）和NMOS晶体管（104），并且公共漏极被配置为防止在电源期间来自电源的Icc电流的大量漏极，向上。为了在上电期间防止大的Icc，PMOS晶体管（102）和NMOS晶体管（104）的阈值电压被设置为使得PMOS晶体管（102）和NMOS晶体管（104）不一起导通，而不管电荷最初存储在浮动门上。没有这样的阈值，电流连接Vcc可以发生电流Icc的显着漏极，因为最初在浮置栅极上的电荷在产生从VCC到Vss的Icc的路径上离开PMOS晶体管（102）和NMOS晶体管（104）。

6. 发明授权

US06636442B2 Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress 失效
标题翻译：具有级联晶体管方案以减少氧化物场应力的非易失性存储元件
公开(公告)号：US06636442B2
公开(公告)日：2003-10-21
申请号：US10059624
申请日：2002-01-29
申请人： Michael Rowlandson , Andrew Horch
发明人： Michael Rowlandson , Andrew Horch
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/3418
摘要： A non-volatile memory cell (FIG. 3) is provided which includes three transistors, a floating gate non-volatile storage transistor (303) and two cascode connected select transistors (301-302). The two cascoded select transistors (301-302) act together to block the programming voltage when the memory cell is included in an array, and the memory cell is not selected for programming. A value of an unselect voltage applied to the gate of the first cascode connected transistor (301) is set to prevent breakdown of the oxide in the first cascode transistor (301) as well as the second cascode transistor (302). A value of an unselect voltage applied to the gate of the second cascode connected transistor (302) can be selected so that the voltage passed to the floating gate storage transistor (303) will not result in a program drain disturb, or source disturb condition.
摘要翻译：提供了一种非易失性存储单元（图3），其包括三个晶体管，一个浮动非易失性非易失性存储晶体管（303）和两个共源共栅连接的选择晶体管（301-302）。当存储器单元包括在阵列中时，两个级联选择晶体管（301-302）一起起作用以阻止编程电压，并且不选择存储单元进行编程。设置施加到第一共源共栅晶体管（301）的栅极的未选择电压的值，以防止第一共源共栅晶体管（301）中的氧化物以及第二共源共栅晶体管（302）的击穿。可以选择施加到第二共源共栅晶体管（302）的栅极的取消选择电压的值，使得传递到浮置栅极存储晶体管（303）的电压不会导致编程漏极干扰或源干扰条件。

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