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1. 发明授权

US06635947B2 Monolithically integrable inductor 失效
公开(公告)号：US06635947B2
公开(公告)日：2003-10-21
申请号：US09934979
申请日：2001-08-21
申请人： Alexander Benedix , Georg Braun , Helmut Fischer , Bernd Klehn , Sebastian Kuhne
发明人： Alexander Benedix , Georg Braun , Helmut Fischer , Bernd Klehn , Sebastian Kuhne
IPC分类号： H01L2900
CPC分类号： G11C11/16 , H01L43/08
摘要： A monolithically integrable inductor containing a layer sequence of conductive layers and insulating layers that are stacked mutually alternately above one another is described. The conductive layers are configured in such a way that they form a coil-type structure around a central region, in which giant magnetic resistance materials can be provided.

2. 发明授权

US07127553B2 Method for determining the optimum access strategy 有权
标题翻译：确定最佳访问策略的方法
公开(公告)号：US07127553B2
公开(公告)日：2006-10-24
申请号：US10717337
申请日：2003-11-19
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： H01L27/108
CPC分类号： G06F11/3409
摘要： A configuration for executing data processing processes has an operating system and various system resources that are accessed by the operating system using an access strategy for the execution of system processes. When there are different applications, different access strategies to the system resources are used. A method is also provided for determining the optimum access strategy to the system resources.
摘要翻译：用于执行数据处理过程的配置具有由操作系统使用用于执行系统进程的访问策略来访问的操作系统和各种系统资源。当有不同的应用程序时，使用与系统资源不同的访问策略。还提供了一种用于确定对系统资源的最佳访问策略的方法。

3. 发明授权

US06820197B2 Data processing system having configurable components 有权
标题翻译：数据处理系统具有可配置的组件
公开(公告)号：US06820197B2
公开(公告)日：2004-11-16
申请号：US10000690
申请日：2001-11-15
申请人： Alexander Benedix , Georg Braun , Bernd Klehn
发明人： Alexander Benedix , Georg Braun , Bernd Klehn
IPC分类号： G06F15177
CPC分类号： G06F9/4411 , G06F15/177
摘要： The data processing system has configurable components, which each have a configuration register for storing configuration data. A serial bus couples the configuration registers to a non-volatile memory so that a serial transmission of data from the non-volatile memory to the configuration registers is made possible, for example when the system is booted up. The system already functions even if complex bus systems, such as extensively parallel high-speed buses, for example, are not yet available in a configuration process of the system. The system can be used in all data processing systems, in particular in mobile applications.
摘要翻译：数据处理系统具有可配置的组件，每个组件具有用于存储配置数据的配置寄存器。串行总线将配置寄存器耦合到非易失性存储器，使得可以例如当系统启动时将数据从非易失性存储器串行传输到配置寄存器。即使在系统的配置过程中，诸如广泛并行的高速总线之类的复杂总线系统尚不可用，该系统也已经起作用。该系统可用于所有数据处理系统，特别是在移动应用中。

4. 发明授权

US07771206B2 Horizontal dual in-line memory modules 有权
标题翻译：水平双列直插式内存模块
公开(公告)号：US07771206B2
公开(公告)日：2010-08-10
申请号：US12209019
申请日：2008-09-11
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gärtner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： H01R12/00
CPC分类号： H05K1/141 , H05K1/144 , H05K3/326 , H05K3/328 , H05K3/366 , H05K3/4092 , H05K2201/0397 , H05K2201/042 , H05K2201/045 , H05K2201/10159 , H05K2203/049
摘要： Horizontal dual in-line memory modules are disclosed. In one embodiment, the memory module includes a circuit board, a plurality of memory chips attached to a top surface of the circuit board, and a plurality of connector contacts disposed under a back surface of the circuit board and extending away from the memory chips, the connector contacts being electrically coupled to the memory chips, the back surface opposite the top surface of the circuit board.
摘要翻译：公开了水平双列直插式存储器模块。在一个实施例中，存储器模块包括电路板，附接到电路板的顶表面的多个存储器芯片以及设置在电路板的背面下方并远离存储器芯片延伸的多个连接器触点，连接器触点电耦合到存储器芯片，背面与电路板的顶表面相对。

5. 发明申请

US20100082871A1 Distributed Command and Address Bus Architecture 有权
标题翻译：分布式命令和地址总线架构
公开(公告)号：US20100082871A1
公开(公告)日：2010-04-01
申请号：US12328690
申请日：2008-12-04
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gartner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gartner , Hermann Ruckerbauer , George William Alexander , Johannes Stecker
IPC分类号： G06F13/00
CPC分类号： G06F13/409
摘要： Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.
摘要翻译：描述了内存模块和电路板的分布式命令和地址总线架构。在一个实施例中，存储器模块包括设置在电路板边缘上的多个连接器引脚，所述多个连接器引脚包括耦合到多个数据总线的第一引脚，耦合到多个命令和地址总线的第二引脚线，其中第二引脚设置在第一和第二区域中，其中第一引脚的一部分设置在第一和第二区域之间。

6. 发明申请

US20100030934A1 Bus Termination System and Method 有权
标题翻译：总线终端系统和方法
公开(公告)号：US20100030934A1
公开(公告)日：2010-02-04
申请号：US12185472
申请日：2008-08-04
申请人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George Alexander , Johannes Stecker
发明人： Michael Bruennert , Peter Gregorius , Georg Braun , Andreas Gaertner , Hermann Ruckerbauer , George Alexander , Johannes Stecker
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/4086
摘要： A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.
摘要翻译：存储器系统包括耦合到总线的多个集成电路芯片。每个集成电路芯片具有耦合到总线的输入/输出节点，该输入/输出节点具有可编程的片上终端电阻器。通过总线访问集成电路芯片之一的输入/输出节点。每个集成电路芯片的可编程片上终端电阻独立地设置为终端电阻。终端电阻由交易类型和正在被访问的多个存储器件中的哪一个确定，哪些信息可以通过单独的传输控制总线传输。

7. 发明授权

US07646650B2 Buffer component for a memory module, and a memory module and a memory system having such buffer component 有权
标题翻译：用于存储器模块的缓冲器组件，以及具有这种缓冲器组件的存储器模块和存储器系统
公开(公告)号：US07646650B2
公开(公告)日：2010-01-12
申请号：US11368267
申请日：2006-03-03
申请人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
发明人： Georg Braun , Srdjan Djordjevic , Andreas Jakobs
IPC分类号： G11C7/10
CPC分类号： G11C5/063 , G06F13/1689 , G11C5/04 , G11C7/1078 , G11C7/109
摘要： A buffer component for a memory module having a plurality of memory components includes item of access information in accordance with a data transmission protocol, the address, clock, control and command signals depending on the access information, a second data interface for driving a clock signal and address and command signals to the plurality of memory components and for driving a control signal to a group of the plurality of memory components in accordance with a signaling protocol, wherein an activation of the memory components and an acceptance of the address and command signals are effected in a manner dependent on the control signals, and a control unit which applies the address and command signals to the plurality of memory components during a first clock period of the clock signal and applies the control signal for activating the group of the plurality of memory components to the group of the plurality of memory components to be activated when address and command signals are present, in a succeeding second clock period of the clock signal, whereby the address and command signals present are accepted into the group of the plurality of memory components.
摘要翻译：具有多个存储器组件的存储器模块的缓冲器组件包括根据数据传输协议的访问信息项，取决于访问信息的地址，时钟，控制和命令信号，用于驱动时钟信号的第二数据接口以及根据信令协议对多个存储器组件的地址和命令信号以及用于将控制信号驱动到一组多个存储器组件，其中存储器组件的激活和地址和命令信号的接受是以取决于控制信号的方式实现;以及控制单元，其在时钟信号的第一时钟周期期间将地址和命令信号施加到多个存储器组件，并施加用于激活多个存储器的组的控制信号当地址和命令信号时，要激活的多个存储器组件的组件的组件存在于时钟信号的随后的第二时钟周期中，由此存在的地址和命令信号被接收到多个存储器组件的组中。

8. 发明申请

US20080155150A1 Apparatus and method for providing a signal for transmission via a signal line 有权
标题翻译：用于提供用于经由信号线传输的信号的装置和方法
公开(公告)号：US20080155150A1
公开(公告)日：2008-06-26
申请号：US11644998
申请日：2006-12-22
申请人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
发明人： Edoardo Prete , Hans-Peter Trost , Anthony Sanders , Dirk Scheideler , Georg Braun , Steve Wood , Richard Johannes Luyken
IPC分类号： G06F13/00
CPC分类号： G06F13/1668
摘要： An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.
摘要翻译：一种用于经由信号线提供用于传输的信号的装置包括控制器电路，其具有用于指示信号线是否将处于非活动状态的信号的输出和耦合到控制器电路的开关电路，并且具有耦合到信号线。如果信号指示信号线处于非活动状态，则输出在不同的信号电平之间切换。

9. 发明授权

US07376802B2 Memory arrangement 失效
标题翻译：内存安排
公开(公告)号：US07376802B2
公开(公告)日：2008-05-20
申请号：US10850382
申请日：2004-05-21
申请人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
发明人： Georg Braun , Hermann Ruckerbauer , Maksim Kuzmenka , Siva Raghuram
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C7/10 , G06F13/1678
摘要： The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.
摘要翻译：本发明涉及一种具有控制器并具有至少一个存储器件的存储器装置。数据信号，控制信号和地址信号可以在控制器和存储器件之间传输。存储器布置被设计成使得数据信号可以通过控制器和存储器件之间的数据信号线传送。此外，存储器布置被设计成使得控制信号和地址信号同样能够经由控制器和存储器件之间的数据信号线传送。

10. 发明申请

US20070133329A1 Integrated semiconductor memory with determination of a chip temperature 失效
标题翻译：集成半导体存储器，具有芯片温度的测定
公开(公告)号：US20070133329A1
公开(公告)日：2007-06-14
申请号：US11635088
申请日：2006-12-07
申请人： Georg Braun , Aaron Nygren
发明人： Georg Braun , Aaron Nygren
IPC分类号： G11C11/34
CPC分类号： G11C7/04 , G11C7/24 , G11C11/4063 , G11C11/4078
摘要： An integrated semiconductor memory capable of determining a chip temperature includes first control terminals for driving the integrated semiconductor memory with first control signals for performing a write access and second control terminals provided for performing a read access. The integrated semiconductor further includes a control circuit for controlling a write and read access. A temperature sensor for recording a chip temperature of the integrated semiconductor memory is connected to the control circuit. The control circuit is configured to generate a state of a third control signal at one of the first or at one of the second control terminals in a manner dependent on a temperature recorded by the temperature sensor.
摘要翻译：能够确定芯片温度的集成半导体存储器包括用于驱动集成半导体存储器的第一控制端子，其具有用于执行写访问的第一控制信号和用于执行读访问的第二控制端。集成半导体还包括用于控制写入和读取访问的控制电路。用于记录集成半导体存储器的芯片温度的温度传感器连接到控制电路。控制电路被配置为以取决于温度传感器记录的温度的方式在第一或第一控制端子中的一个处产生第三控制信号的状态。

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