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1. 发明申请

US20090289668A1 Output driver circuit for an integrated circuit 审中-公开
标题翻译：用于集成电路的输出驱动电路
公开(公告)号：US20090289668A1
公开(公告)日：2009-11-26
申请号：US12153792
申请日：2008-05-23
申请人： Alberto Baldisserotto , Steven Broome , Jason Thurston , Carl Thomas Gray
发明人： Alberto Baldisserotto , Steven Broome , Jason Thurston , Carl Thomas Gray
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H03K19/09432
摘要： An integrated circuit 2 is provided with an output driver circuit 12. The output driver circuit 12 one side provides between a first power supply 20 and a second power supply 18 a first transistor 16, a first output 22, a first resistor 14 and, connected in parallel with the first resistor 14, a first bypass transistor 24. The first bypass transistor 24 is controlled by a first bypass control voltage vbp such that as the first output voltage of the first output 22 approaches the second power supply voltage of the second power supply 18, the first bypass transistor 24 serves to bypass the first resistor 14 and provide a single-ended impedance of the output driver circuit 12 which approximates to zero. On the complementary side of the output driver circuit 12 there are similarly provided a second transistor 28, a second resistor 26 and a bypass transistor 32.
摘要翻译：集成电路2设置有输出驱动器电路12.输出驱动器电路12一侧提供第一电源20和第二电源18之间的第一晶体管16，第一输出22，第一电阻14和连接与第一电阻器14并联，第一旁路晶体管24.第一旁路晶体管24由第一旁路控制电压vbp控制，使得当第一输出端22的第一输出电压接近第二电源的第二电源电压时电源18，第一旁路晶体管24用于旁路第一电阻器14，并提供近似为零的输出驱动器电路12的单端阻抗。在输出驱动器电路12的互补侧，类似地提供第二晶体管28，第二电阻26和旁路晶体管32。

2. 发明申请

US20090290626A1 Programmable duty cycle distortion generation circuit 有权
标题翻译：可编程占空比失真发生电路
公开(公告)号：US20090290626A1
公开(公告)日：2009-11-26
申请号：US12153796
申请日：2008-05-23
申请人： Jason Thurston , Carl Thomas Gray
发明人： Jason Thurston , Carl Thomas Gray
IPC分类号： H04B3/46
CPC分类号： H04B3/462 , G01R31/31708 , G01R31/31715
摘要： An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.
摘要翻译：提供一种集成电路，包括：串行发送器，串行接收器和串行连接，提供串行发送器和串行接收器之间的通信。集成电路还包括占空比失真电路，使得可以通过使集成电路内的信号的占空比失真来对集成电路进行压力测试。

3. 发明申请

US20090292962A1 Integrated circuit with inter-symbol interference self-testing 审中-公开
标题翻译：具有符号间干扰自检的集成电路
公开(公告)号：US20090292962A1
公开(公告)日：2009-11-26
申请号：US12153794
申请日：2008-05-23
申请人： Jason Thurston , Carl Thomas Gray
发明人： Jason Thurston , Carl Thomas Gray
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/31716
摘要： An integrated circuit 2 having a data receiver circuit 14 for a serial data signal also includes a test data generating circuit 24 for self-test purposes. The test generating circuit includes a filter circuit 230, 32, 34, 36 which processes an input test serial data signal to generate an output test serial data signal having enhanced inter-symbol interference for loopback to the data receiver circuit so as to test that data receiver circuit.
摘要翻译：具有用于串行数据信号的数据接收器电路14的集成电路2还包括用于自检目的的测试数据产生电路24。测试产生电路包括滤波器电路230,32,34,36，其处理输入的测试串行数据信号以产生具有增强的符号间干扰的输出测试串行数据信号，用于环回到数据接收器电路，以便测试该数据接收电路。

4. 发明申请

US20090290624A1 Programmable jitter generation circuit 审中-公开
标题翻译：可编程抖动生成电路
公开(公告)号：US20090290624A1
公开(公告)日：2009-11-26
申请号：US12153801
申请日：2008-05-23
申请人： Jason Thurston , Carl Thomas Gray , Terry Perkinson
发明人： Jason Thurston , Carl Thomas Gray , Terry Perkinson
IPC分类号： H04B1/38
CPC分类号： G01R31/31709
摘要： The present invention provides an integrated circuit comprising a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The serial transmitter comprises a clock generator and a serializer for serializing data to be transmitted to the serial receiver. A clock control unit coupled to the clock generator alters the clock phase of the clock signal to stress test the serial receiver.
摘要翻译：本发明提供一种集成电路，其包括串行发送器，串行接收器和提供串行发送器和串行接收器之间的通信的串行连接。串行发送器包括时钟发生器和串行器，用于串行化要发送到串行接收器的数据。耦合到时钟发生器的时钟控制单元改变时钟信号的时钟相位，以对串行接收器进行压力测试。

5. 发明授权

US08194721B2 Signal amplitude distortion within an integrated circuit 有权
标题翻译：集成电路内的信号幅度失真
公开(公告)号：US08194721B2
公开(公告)日：2012-06-05
申请号：US12153793
申请日：2008-05-23
申请人： Carl Thomas Gray , Jason Thurston
发明人： Carl Thomas Gray , Jason Thurston
IPC分类号： H04B17/00
CPC分类号： H04L1/243
摘要： An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.
摘要翻译：集成电路2包括串行数据发送器12和串行数据接收器14.提供信号幅度失真电路30以引入由串行数据发送器12产生的串行数据信号的幅度的失真并循环回到串行数据接收器14，以便对串行数据接收器14进行压力测试。

6. 发明授权

US08179952B2 Programmable duty cycle distortion generation circuit 有权
标题翻译：可编程占空比失真发生电路
公开(公告)号：US08179952B2
公开(公告)日：2012-05-15
申请号：US12153796
申请日：2008-05-23
申请人： Jason Thurston , Carl Thomas Gray
发明人： Jason Thurston , Carl Thomas Gray
IPC分类号： H04B3/46
CPC分类号： H04B3/462 , G01R31/31708 , G01R31/31715
摘要： An integrated circuit is provided comprising: a serial transmitter, a serial receiver and a serial connection providing communication between the serial transmitter and the serial receiver. The integrated circuit further comprises a duty cycle distortion circuit so that the integrated circuit can be stress tested by distorting the duty cycle of a signal within the integrated circuit.
摘要翻译：提供一种集成电路，包括：串行发送器，串行接收器和串行连接，提供串行发送器和串行接收器之间的通信。集成电路还包括占空比失真电路，使得可以通过使集成电路内的信号的占空比失真来对集成电路进行压力测试。

7. 发明申请

US20090292961A1 Integrated circuit communication self-testing 有权
标题翻译：集成电路通信自检
公开(公告)号：US20090292961A1
公开(公告)日：2009-11-26
申请号：US12153795
申请日：2008-05-23
申请人： Jason Thurston , Carl Thomas Gray
发明人： Jason Thurston , Carl Thomas Gray
IPC分类号： G01R31/3183 , G06F11/263
CPC分类号： G01R31/31715
摘要： An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.
摘要翻译：集成电路2包括多个串行数据发送器18和多个串行数据接收器20.提供具有相关片上测试电路24,26,28的片上测试信号路径22，以便允许片上串行数据通信将由片上测试电路24,26,28施加的测试特性进行，由此提供数据发射机18和串行数据接收机20的片上压力测试。

8. 发明申请

US20090290623A1 Signal amplitude distortion within an integrated circuit 有权
标题翻译：集成电路内的信号幅度失真
公开(公告)号：US20090290623A1
公开(公告)日：2009-11-26
申请号：US12153793
申请日：2008-05-23
申请人： Carl Thomas Gray , Jason Thurston
发明人： Carl Thomas Gray , Jason Thurston
IPC分类号： H04B17/00
CPC分类号： H04L1/243
摘要： An integrated circuit 2 includes a serial data transmitter 12 and a serial data receiver 14. A signal amplitude distorting circuit 30 is provided to introduce distortion in the amplitude of a serial data signal generated by the serial data transmitter 12 and looped back to the serial data receiver 14 so as to stress test the serial data receiver 14.
摘要翻译：集成电路2包括串行数据发送器12和串行数据接收器14.提供信号幅度失真电路30以引入由串行数据发送器12产生的串行数据信号的幅度的失真并循环回到串行数据接收器14，以便对串行数据接收器14进行压力测试。

9. 发明授权

US07770078B2 Integrated circuit communication self-testing 有权
标题翻译：集成电路通信自检
公开(公告)号：US07770078B2
公开(公告)日：2010-08-03
申请号：US12153795
申请日：2008-05-23
申请人： Jason Thurston , Carl Thomas Gray
发明人： Jason Thurston , Carl Thomas Gray
IPC分类号： G01R31/28
CPC分类号： G01R31/31715
摘要： An integrated circuit 2 includes a plurality of serial data transmitters 18 and a plurality of serial data receivers 20. On-chip test signal paths 22 with associated on-chip test circuits 24, 26, 28 are provided so as to permit on-chip serial data communication to be performed with test characteristics imposed by the on-chip test circuits 24, 26, 28 thereby providing on-chip stress testing of the data transmitter 18 and the serial data receiver 20.
摘要翻译：集成电路2包括多个串行数据发送器18和多个串行数据接收器20.提供具有相关片上测试电路24,26,28的片上测试信号路径22，以便允许片上串行数据通信将由片上测试电路24,26,28施加的测试特性进行，由此提供数据发射机18和串行数据接收机20的片上压力测试。

10. 发明授权

US06222380B1 High speed parallel/serial link for data communication 有权
标题翻译：用于数据通信的高速并行/串行链路
公开(公告)号：US06222380B1
公开(公告)日：2001-04-24
申请号：US09330968
申请日：1999-06-11
申请人： Robert Glen Gerowitz , Carl Thomas Gray , John Marshall , Christopher G. Riedle , Raymond Paul Rizzo
发明人： Robert Glen Gerowitz , Carl Thomas Gray , John Marshall , Christopher G. Riedle , Raymond Paul Rizzo
IPC分类号： H03K19173
CPC分类号： H03M9/00 , C22C21/08 , C22F1/047 , C22F1/05
摘要： An interface system that conveys data at approximately 500 MBitsps between modules. The interface system performs multistream serialization at the transmitter and multistream de-serialization at the Receiver. As a consequence, fewer interface connections are required between the modules.
摘要翻译：一个接口系统，可在模块之间传输大约500 MB的数据。接口系统在发射机处执行多流串行化，并在接收机处执行多流逆序列化。因此，模块之间需要更少的接口连接。

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