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    • 1. 发明申请
    • In-circuit programming architecture with processor, delegable flash controller, and code generator
    • 具有处理器,委托闪存控制器和代码生成器的在线编程架构
    • US20060041712A1
    • 2006-02-23
    • US10924400
    • 2004-08-23
    • Albert SunJeon-Yung RayWilliam Chen
    • Albert SunJeon-Yung RayWilliam Chen
    • G06F12/00
    • G06F8/65
    • An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a microprocessor and control logic on an integrated circuit having a single non-volatile memory that stores instructions and data, such as in-circuit programming and user code, and input/output ports and related structure for exchanging data with an external device. Using in-circuit programming code stored on the chip, the chip interactively establishes an in-circuit programming exchange with an external device to update data and instructions including the in-circuit programming code. Input/output conflicts during in-circuit programming can be avoided by employing a code generator that supplies control routines to the microprocessor during at least part of the in-circuit programming operations. The code generator allows the in-circuit programming code to be updated in real time.
    • 具有在线编程的集成电路架构允许实时修改存储在芯片上的在线编程代码和其他代码。 该架构在具有存储指令和数据的单个非易失性存储器的集成电路中使用微处理器和控制逻辑,诸如在线编程和用户代码以及用于与外部设备交换数据的输入/输出端口和相关结构 。 使用存储在芯片上的在线编程代码,芯片与外部设备交互地建立在线编程交换,以更新包括在线编程代码的数据和指令。 可以通过在至少部分在线编程操作期间使用向微处理器提供控制程序的代码生成器来避免在线编程期间的输入/输出冲突。 代码生成器允许在线编程代码实时更新。
    • 4. 发明授权
    • Voltage stabilizer of embedded flash memory
    • 嵌入式闪存的稳压器
    • US06388923B1
    • 2002-05-14
    • US09829290
    • 2001-04-09
    • Jew-Yong KuoAlbert Sun
    • Jew-Yong KuoAlbert Sun
    • G11C1604
    • G11C16/30G11C2207/104
    • A voltage stabilizer of an embedded flash memory to modulate an input voltage VDD with a wide range of variation to a fixed voltage as an output. The voltage at the bit line of the selected memory cell can be fixed to avoid error access. The voltage stabilizer of the embedded flash memory performs a voltage range inspection using a voltage inspector. Comparing to a standard value, an input voltage higher or lower than the standard value is output from a first terminal or a second terminal, respectively. The input voltage output from the first or second terminals is then stabilized to output a fixed voltage.
    • 嵌入式闪速存储器的稳压器,用于调制具有宽的变化范围的输入电压VDD作为输出的固定电压。 所选存储单元的位线处的电压可以被固定以避免错误访问。 嵌入式闪存的稳压器使用电压检查器进行电压范围检查。 与标准值相比,分别从第一端子或第二端子输出高于或低于标准值的输入电压。 然后从第一或第二端子输出的输入电压被稳定以输出固定电压。
    • 8. 发明授权
    • Stable frequency clock generator
    • 稳定的频率时钟发生器
    • US06384656B1
    • 2002-05-07
    • US09829222
    • 2001-04-09
    • Jew-Yong KuoAlbert Sun
    • Jew-Yong KuoAlbert Sun
    • H03K300
    • H03K3/0231H03K3/03H03K3/0322
    • A fixed frequency clock generator generates and outputs a fixed frequency clock by using a number of fixed delay units and a number of inverters that both are connected in series alternately and evenly. More particularly, the fixed delay unit involves two fixed current sources and two controlling switchers, plus an inverter that controls a charging and a discharging of a capacitor. Then the electric potential of the capacitor and a stable voltage source respectively send the current to the comparator. The time of charging and discharging of the capacitor is fixed, therefore the time of the electric potential of the capacitor is fixed for reach to the fixed voltage source, and the sequence of the output signal of the comparator is also fixed. In the above description, the fixed delay unit generates the fixed frequency.
    • 固定频率时钟发生器通过使用多个固定延迟单元和多个逆变器交替且均匀地串联连接而产生并输出固定频率时钟。 更具体地,固定延迟单元包括两个固定电流源和两个控制切换器,以及控制电容器的充电和放电的逆变器。 然后电容器的电位和稳定的电压源分别将电流发送到比较器。 电容器的充放电时间是固定的,因此电容器的电位的时间是固定的,以达到固定电压源,并且比较器的输出信号的顺序也是固定的。 在上述说明中,固定延迟单元产生固定频率。