专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6014044A Voltage comparator with floating gate MOS transistor 失效
标题翻译：具有浮动栅极MOS晶体管的电压比较器
公开(公告)号：US6014044A
公开(公告)日：2000-01-11
申请号：US960186
申请日：1997-10-29
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Philip Leong , Marco Onorato , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Philip Leong , Marco Onorato , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： H03K5/08 , H03K19/00 , H03M1/36 , H03M1/46 , H03K5/153
CPC分类号： H03K5/08 , H03K19/0027 , H03M1/36 , H03M1/46
摘要： This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.
摘要翻译：本发明涉及具有用于模拟信号和数字信号的输出的电压比较器，包括一个反相器，该反相器具有耦合到比较器输入的输入端和耦合到该比较器输出的输出，并且包括至少两个MOS晶体管彼此耦合，两个MOS晶体管中的至少一个是浮栅型。

2. 发明授权

US5946235A Floating gate MOS transistor charge injection circuit and computation devices incorporating it 失效
标题翻译：浮栅MOS晶体管电荷注入电路和结合其的计算器件
公开(公告)号：US5946235A
公开(公告)日：1999-08-31
申请号：US940278
申请日：1997-09-30
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： G06G7/26 , G06N3/063 , G11C16/04
CPC分类号： G11C16/0441 , G06G7/26 , G06N3/0635
摘要： The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.
摘要翻译：本发明的电荷注入电路包括至少一对浮置栅极MOS晶体管，其具有耦合在一起并且连接到注入节点的源极和漏极端子以及具有基本上阶梯状电压信号的至少一对相应的发生器，其具有初始值和最终值，并且具有分别耦合到所述晶体管的控制端子的输出。信号发生器使得第一信号的初始值基本上等于第二信号的最终值，并且第一信号的最终值基本上等于第二信号的初始值信号。

3. 发明授权

US5880993A Method and circuit for checking multilevel programming of floating-gate nonvolatile memory cells particularly flash cells 失效
标题翻译：用于检查浮栅非易失性存储单元特别是闪存单元的多级编程的方法和电路
公开(公告)号：US5880993A
公开(公告)日：1999-03-09
申请号：US941882
申请日：1997-09-30
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： G01R31/28 , G11C11/56 , G11C16/02 , G11C16/34 , G11C29/12 , G11C29/50 , G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C16/3459 , G11C16/3468 , G11C16/3481 , G11C27/005 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2211/5621 , G11C2211/5624
摘要： To check the programming of a nonvolatile memory cell storing an actual threshold value, the drain terminal of the cell is biased at a constant voltage; the gate terminal is biased at a check voltage; the cell is supplied with a predetermined current to determine a gate-source voltage drop related to the actual threshold value; and the voltage at the source terminal is supplied to an input of an operational amplifier. In an open-loop configuration, the desired threshold value of the set predetermined current is supplied as the check voltage; the amplifier compares the source voltage with the ground; and switching of the amplifier indicates the desired threshold value has been reached. In a closed-loop configuration, the output of the operational amplifier is connected directly to the gate terminal of the cell, and supplies the desired threshold value directly.
摘要翻译：为了检查存储实际阈值的非易失性存储单元的编程，单元的漏极端子被偏置为恒定电压; 栅极端子被偏置在检查电压; 向单元提供预定电流以确定与实际阈值相关的栅极 - 源极电压降; 并且源极端子处的电压被提供给运算放大器的输入端。在开环配置中，将所设定的预定电流的期望阈值作为检查电压被提供; 放大器将源电压与地相比较; 并且放大器的切换指示已经达到期望的阈值。在闭环配置中，运算放大器的输出直接连接到单元的栅极端，并直接提供所需的阈值。

4. 发明授权

US5990816A Digital-to-analog current converter employing floating gate MOS transistors 失效
标题翻译：采用浮栅MOS晶体管的数模转换电流转换器
公开(公告)号：US5990816A
公开(公告)日：1999-11-23
申请号：US940803
申请日：1997-09-30
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Philip Leong , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Philip Leong , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： H03M1/74 , H03M1/00
CPC分类号： H03M1/74
摘要： The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals and an output for an analog signal. It comprises a current amplification circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference of potential. The converter has drain terminals coupled together and to the input of the amplification circuit, and has control terminals coupleable, under control from the inputs of the plurality, to different references of potential having selected fixed values.
摘要翻译：本发明涉及具有用于数字信号的多个输入和用于模拟信号的输出的数模转换器。它包括具有耦合到转换器输出的输入和输出的电流放大电路，以及对应于多个转换器输入并且其源极端子耦合在一起并具有第一潜在参考电压的多个浮置栅极MOS晶体管。该转换器具有耦合到放大电路的输入端的漏极端子，并且在多个输入端的控制下具有可耦合的控制端子到具有选定的固定值的不同的电位基准。

5. 发明授权

US5973949A Input structure for analog or digital associative memories 失效
标题翻译：模拟或数字关联存储器的输入结构
公开(公告)号：US5973949A
公开(公告)日：1999-10-26
申请号：US941879
申请日：1997-09-30
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/00 , G11C15/046
摘要： An input structure for associative memories, including an array of elementary cells, a number of input lines, a number of output lines, a number of address lines, and a number of enable lines. Each elementary cell is formed by a D flip-flop having a data input coupled to one of the address lines and an enable input coupled to one of the enable lines, and by a switch coupled between an input line and an output line, and having a control input coupled to the output of a respective latch to selectively couple the respective input line and output line according to the data stored in the latch.
摘要翻译：一种用于关联存储器的输入结构，包括基本单元阵列，输入线数量，输出线数量，地址线数量以及使能线数。每个单元由D触发器形成，D触发器具有耦合到一个地址线的数据输入和耦合到使能线之一的使能输入，以及耦合在输入线和输出线之间的开关，并且具有耦合到相应锁存器的输出的控制输入，以根据存储在锁存器中的数据选择性地耦合相应的输入线和输出线。

6. 发明授权

US5952946A Digital-to-analog charge converter employing floating gate MOS transisitors 失效
标题翻译：采用浮栅MOS晶体管的数模转换电荷转换器
公开(公告)号：US5952946A
公开(公告)日：1999-09-14
申请号：US941881
申请日：1997-09-30
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： H03M1/80 , H03M1/66
CPC分类号： H03M1/802
摘要： The present invention relates to a digital-to-analog converter having a plurality of inputs for digital signals, and an output for an analog signal. It also contains a charge integration circuit having an input and an output coupled to the converter output, and a plurality of floating gate MOS transistors corresponding to the plurality of converter inputs, the MOS transistors all having their source and drain terminals coupled together and to the input of the integration circuit, and having control terminals coupleable, under control from the plurality of inputs of digital signals, to different reference voltages having selected fixed values.
摘要翻译：本发明涉及具有用于数字信号的多个输入和用于模拟信号的输出的数模转换器。它还包含具有耦合到转换器输出的输入和输出的电荷积分电路，以及与多个转换器输入相对应的多个浮置栅极MOS晶体管，所述MOS晶体管的源极和漏极端子都耦合在一起并连接到输入积分电路，并且在多个数字信号输入的控制下使控制端可耦合到具有选定的固定值的不同参考电压。

7. 发明授权

US5901085A Programmable reference voltage source, particularly for analog memories 失效
标题翻译：可编程参考电压源，特别适用于模拟存储器
公开(公告)号：US5901085A
公开(公告)日：1999-05-04
申请号：US941880
申请日：1997-09-30
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： G11C16/06 , G05F1/56 , G11C27/00 , G11C16/04
CPC分类号： G11C27/005
摘要： A programmable reference voltage source includes a nonvolatile memory cell, the floating-gate region of which stores electric charges determining a memorized threshold value. The drain terminal of the cell is biased at a constant voltage, and the source terminal is coupled to a constant-current source and to the inverting input of an operational amplifier having the noninverting input coupled to a reference voltage and the output coupled to the gate terminal of the cell. By defining the threshold of the cell as the gate voltage (measured with respect to ground) capable of causing the cell to be flown by the current set by the current source, the output voltage of the operational amplifier equals the threshold and may be used as a programmable reference in analog memories.
摘要翻译：可编程参考电压源包括非易失性存储单元，其浮动栅极区域存储确定存储的阈值的电荷。电池的漏极端子以恒定电压被偏置，并且源极端子耦合到恒定电流源和运算放大器的反相输入端，该运算放大器具有耦合到参考电压的非反相输入端，耦合到栅极的输出端终端的单元格。通过将电池的阈值定义为能够使电池流过由电流源设定的电流的栅极电压（相对于地测量），运算放大器的输出电压等于阈值，并且可以用作模拟存储器中的可编程参考。

8. 发明授权

US06252802B1 Floating gate MOS transistor charge injection circuit and computation devices incorporating it 有权
公开(公告)号：US06252802B1
公开(公告)日：2001-06-26
申请号：US09636397
申请日：2000-08-09
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： G11C700
CPC分类号： G11C16/0441 , G06G7/26 , G06N3/0635
摘要： The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

9. 发明授权

US06236592B1 Floating gate MOS transistor charge injection circuit and computation devices incorporating it 有权
标题翻译：浮栅MOS晶体管电荷注入电路和结合其的计算器件
公开(公告)号：US06236592B1
公开(公告)日：2001-05-22
申请号：US09373813
申请日：1999-08-13
申请人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
发明人： Alan Kramer , Roberto Canegallo , Mauro Chinosi , Giovanni Gozzini , Pier Luigi Rolandi , Marco Sabatini
IPC分类号： G11C1300
CPC分类号： G11C16/0441 , G06G7/26 , G06N3/0635
摘要： The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.
摘要翻译：本发明的电荷注入电路包括至少一对浮置栅极MOS晶体管，其具有耦合在一起并且连接到注入节点的源极和漏极端子以及具有基本上阶梯状电压信号的至少一对相应的发生器，其具有初始值和最终值，并且具有分别耦合到所述晶体管的控制端子的输出。信号发生器使得第一信号的初始值基本上等于第二信号的最终值，并且第一信号的最终值基本上等于第二信号的初始值信号。

10. 发明授权

US6163483A Circuit for parallel programming nonvolatile memory cells, with adjustable programming speed 有权
标题翻译：并行编程电路非易失性存储单元，具有可编程速度
公开(公告)号：US6163483A
公开(公告)日：2000-12-19
申请号：US447531
申请日：1999-11-23
申请人： Marco Pasotti , Roberto Canegallo , Giovanni Guaitini , Pier Luigi Rolandi
发明人： Marco Pasotti , Roberto Canegallo , Giovanni Guaitini , Pier Luigi Rolandi
IPC分类号： G11C16/12 , G11C7/00
CPC分类号： G11C16/12
摘要： A circuit having a current mirror circuit with a first node and a second node connected, respectively, to a controllable current source and to a common node connected to the drain terminals of selected memory cells. A first operational amplifier has inputs connected to the first node and the second node, and an output connected to a control terminal of the selected memory cells and forming the circuit output. A second operational amplifier has a first input connected to a ramp generator, a second input connected to the circuit output, and an output connected to a control input of the controllable current source. Thereby, two negative feedback loops keep the drain terminals of the selected memory cells at a voltage value sufficient for programming, and feed the control terminal of the memory cells with a ramp voltage that causes writing of the selected memory cells. The presence of a bias source between the second node and the common node enables use of the same circuit also during reading.
摘要翻译：一种具有电流镜电路的电路，具有第一节点和第二节点，分别连接到可控电流源和连接到所选存储器单元的漏极端子的公共节点。第一运算放大器具有连接到第一节点和第二节点的输入，以及连接到所选择的存储器单元的控制端子并形成电路输出的输出。第二运算放大器具有连接到斜坡发生器的第一输入端，连接到电路输出端的第二输入端，以及连接到可控电流源的控制输入端的输出端。因此，两个负反馈环路将所选择的存储单元的漏极端子保持在足以编程的电压值，并且以导致所选择的存储单元写入的斜坡电压馈送存储单元的控制端子。在第二节点和公共节点之间存在偏置源，使得在读取期间也可以使用相同的电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式