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    • 2. 发明申请
    • Segmented complex diffraction gratings
    • 分段复杂衍射光栅
    • US20050231804A1
    • 2005-10-20
    • US11145251
    • 2005-06-03
    • Thomas MossbergMichael MunroeAnders Grunnet-JepsenAlan JohnsonEric Maniloff
    • Thomas MossbergMichael MunroeAnders Grunnet-JepsenAlan JohnsonEric Maniloff
    • G02B5/18G02B6/34G02B27/42G02B27/44G02B27/46
    • G02B5/1823G02B5/1819G02B6/29311G02B27/4244H04J14/005
    • A structure (i.e. a segmented grating) which applies a designated complex-valued spectral filtering function to the input optical field and emits a filtered version of the input field in an output direction and a method for making such a structure. The segmented gratings fabricated in accordance with the present invention consist of a series of spatially distinct subgratings arrayed end to end. Each subgrating possesses a periodic array of diffraction structures (lines or more general elements). The overall transfer function of the segmented grating is determined by controlling (a) the spatial periodicity or frequency of each subgrating, (b) the amplitude of each subgrating, (c) the spacing between the last diffraction structure (or line) on each subgrating and the first diffraction structure (or line) of the successive subgrating, and (d) the optical path length and transparency through each subgrating, or each subgrating plus additional material layers utilized to control optical path length and transparency.
    • 一种结构(即,分段光栅),其向输入光场施加指定的复值频谱滤波函数,并且在输出方向上发射输入场的滤波版本以及用于制造这种结构的方法。 根据本发明制造的分段光栅由端到端排列的一系列空间上不同的亚格子组成。 每个子格栅具有衍射结构的周期性阵列(线或更一般的元素)。 通过控制(a)每个子格栅的空间周期或频率,(b)每个亚格子化的幅度,(c)每个亚格子化的最后衍射结构(或线)之间的间距来确定分段光栅的总传递函数 以及(d)通过每个亚格子化的光路长度和透明度,或每个亚光加上用于控制光程长度和透明度的附加材料层的第一衍射结构(或线)。
    • 4. 发明申请
    • Segmented complex diffraction gratings
    • 分段复杂衍射光栅
    • US20050225860A1
    • 2005-10-13
    • US11144583
    • 2005-06-03
    • Thomas MossbergMichael MunroeAnders Grunnet-JepsenAlan JohnsonEric Maniloff
    • Thomas MossbergMichael MunroeAnders Grunnet-JepsenAlan JohnsonEric Maniloff
    • G02B5/18G02B6/34G02B27/42G02B27/44G02B27/46
    • G02B5/1823G02B5/1819G02B6/29311G02B27/4244H04J14/005
    • A structure (i.e. a segmented grating) which applies a designated complex-valued spectral filtering function to the input optical field and emits a filtered version of the input field in an output direction and a method for making such a structure. The segmented gratings fabricated in accordance with the present invention consist of a series of spatially distinct subgratings arrayed end to end. Each subgrating possesses a periodic array of diffraction structures (lines or more general elements). The overall transfer function of the segmented grating is determined by controlling (a) the spatial periodicity or frequency of each subgrating, (b) the amplitude of each subgrating,(c) the spacing between the last diffraction structure (or line) on each subgrating and the first diffraction structure (or line) of the successive subgrating, and (d) the optical path length and transparency through each subgrating, or each subgrating plus additional material layers utilized to control optical path length and transparency.
    • 一种结构(即,分段光栅),其向输入光场施加指定的复值频谱滤波函数,并且在输出方向上发射输入场的滤波版本以及用于制造这种结构的方法。 根据本发明制造的分段光栅由端到端排列的一系列空间上不同的亚格子组成。 每个子格栅具有衍射结构的周期性阵列(线或更一般的元素)。 通过控制(a)每个子格栅的空间周期或频率,(b)每个亚格子化的幅度,(c)每个亚格子化的最后衍射结构(或线)之间的间距来确定分段光栅的总传递函数 以及(d)通过每个亚格子化的光路长度和透明度,或每个亚光加上用于控制光程长度和透明度的附加材料层的第一衍射结构(或线)。
    • 7. 发明申请
    • Method and apparatus for aligning multiple outputs of an FPGA
    • 用于对准FPGA的多个输出的方法和装置
    • US20080222594A1
    • 2008-09-11
    • US11716187
    • 2007-03-09
    • Eric ManiloffRonald GagnonBlake Toplis
    • Eric ManiloffRonald GagnonBlake Toplis
    • H03K17/693
    • H03K19/1731H03K19/17744H04L25/14
    • Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.
    • 可以独立地训练连接到FPGA并形成SFI通道的一部分的每个数据通道,以使来自FPGA的输出能够对准。 在操作中,除了正在训练的数据通道之外,在每个数据通道上重复已知的固定模式。 短的固定模式小于SERDES捕获范围,以便SERDES可能暂时锁定到除被训练的通道之外的所有数据通道的短固定模式。 然后训练数据在被训练的车道上传送,并且调整该车道的预定时延,直到接收组件指示车道对齐。 该过程可以迭代以找到所有车道的可接受的前置时间延迟值。 通过一次训练车道并在未经训练的车道上使用短暂的重复模式,SERDES可以注册未经训练的车道正常运行,以便来自SERDES的反馈仅与被训练的车道相关。