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1. 发明授权

US08724283B1 A.C. power line surge protectors 有权
标题翻译：电源线浪涌保护器
公开(公告)号：US08724283B1
公开(公告)日：2014-05-13
申请号：US13341983
申请日：2011-12-31
申请人： Donna M. Auguste , David E. Hayes , Klaus J. Dimmler , Alan D. DeVilbiss
发明人： Donna M. Auguste , David E. Hayes , Klaus J. Dimmler , Alan D. DeVilbiss
IPC分类号： H02H3/22
CPC分类号： H02H3/22 , H02H3/025 , H02H9/041
摘要： In an embodiment, set forth by way of example and not limitation, a power line surge protector circuit includes a first input node, a second input node, a first output node and a second output node; a semiconductor shunt having an avalanche breakdown potential, the shunt being coupled between the first input node and the second input node, whereby a voltage potential between the first input node and the second input node which is in excess of the avalanche breakdown potential shunts current between the first input node and the second input node; and a resettable circuit breaker coupled between the first input node and the shunt.
摘要翻译：在一个实施例中，通过示例而非限制的方式，电力线浪涌保护器电路包括第一输入节点，第二输入节点，第一输出节点和第二输出节点; 具有雪崩击穿电位的半导体分流器，所述分流器耦合在所述第一输入节点和所述第二输入节点之间，由此所述第一输入节点和所述第二输入节点之间的电压电压超过所述雪崩击穿电位，第一输入节点和第二输入节点; 以及耦合在第一输入节点和分流器之间的可复位断路器。

2. 发明授权

US06900536B1 Method for producing an electrical circuit 失效
标题翻译：电路制造方法
公开(公告)号：US06900536B1
公开(公告)日：2005-05-31
申请号：US10132939
申请日：2002-04-26
申请人： Gary F. Derbenwick , Alan D. DeVilbiss
发明人： Gary F. Derbenwick , Alan D. DeVilbiss
IPC分类号： G06K19/077 , H01L20060101 , H01L21/44 , H01L23/34 , H01L23/498 , H05K1/18 , H05K5/00
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译：通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层之一的至少一部分上沉积介电层，将集成电路（IC）安装在衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。内部导电层可以用于将IC耦合到导电层。

3. 发明授权

US07542315B2 Active rectifier 失效
标题翻译：有源整流器
公开(公告)号：US07542315B2
公开(公告)日：2009-06-02
申请号：US11564932
申请日：2006-11-30
申请人： Alan D. DeVilbiss
发明人： Alan D. DeVilbiss
IPC分类号： H02M5/42 , H02M7/04 , H02M7/68
CPC分类号： H02M7/217
摘要： A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.
摘要翻译：电压信号整流器从输入偏移电压信号产生整流电压信号。电压信号整流器包括输入偏移，输出和参考节点，两个主动控制的电流调节元件（ACCRE）和两个控制器。输入偏移节点耦合到输入偏移电压信号。整流电压信号被产生到输出节点上。参考节点耦合到用于输入偏移和整流电压信号的参考电压。 ACCRE耦合到输入偏移节点，并且ACCRE中的一个耦合到输出节点。每个控制器被配置为控制ACCRE中的一个，使得当输入偏移电压信号高于整流电压信号时，耦合到输出节点的ACCRE允许电流流过它，而另一个ACCRE被配置为允许电流流过它当输入失调电压信号低于整流电压信号时。

4. 发明申请

US20080130338A1 Active Rectifier 失效
标题翻译：有源整流器
公开(公告)号：US20080130338A1
公开(公告)日：2008-06-05
申请号：US11564932
申请日：2006-11-30
申请人： Alan D. DeVilbiss
发明人： Alan D. DeVilbiss
IPC分类号： H02M7/217
CPC分类号： H02M7/217
摘要： A voltage signal rectifier produces a rectified voltage signal from an input offset voltage signal. The voltage signal rectifier includes input offset, output, and reference nodes, two actively controlled current regulation elements (ACCREs), and two controllers. The input offset node is coupled to the input offset voltage signal. The rectified voltage signal is generated onto the output node. The reference node is coupled to a reference voltage for the input offset and rectified voltage signals. The ACCREs are coupled to the input offset node and one of the ACCREs is coupled to the output node. Each controller is configured to control the one of the ACCREs so that the ACCRE coupled to the output node allows current flow through it when the input offset voltage signal is higher than the rectified voltage signal and the other ACCRE is configured to allows current flow through it when the input offset voltage signal is lower than the rectified voltage signal.
摘要翻译：电压信号整流器从输入偏移电压信号产生整流电压信号。电压信号整流器包括输入偏移，输出和参考节点，两个主动控制的电流调节元件（ACCRE）和两个控制器。输入偏移节点耦合到输入偏移电压信号。整流电压信号被产生到输出节点上。参考节点耦合到用于输入偏移和整流电压信号的参考电压。 ACCRE耦合到输入偏移节点，并且ACCRE中的一个耦合到输出节点。每个控制器被配置为控制ACCRE中的一个，使得当输入偏移电压信号高于整流电压信号时，耦合到输出节点的ACCRE允许电流流过它，而另一个ACCRE被配置为允许电流流过它当输入失调电压信号低于整流电压信号时。

5. 发明申请

US20080129268A1 Dual Voltage Power Supply 审中-公开
标题翻译：双电压电源
公开(公告)号：US20080129268A1
公开(公告)日：2008-06-05
申请号：US11564989
申请日：2006-11-30
申请人： Alan D. DeVilbiss
发明人： Alan D. DeVilbiss
IPC分类号： G05F1/10 , H02J7/00
CPC分类号： H02J7/345 , H02M7/06
摘要： A power supply for an integrated circuit has first and second energy storage elements and a regulator. The first energy storage element stores energy for application to the integrated circuit. The second energy storage element stores energy at a higher voltage than the energy stored by the first energy storage element. The regulator interconnects the energy storage elements and controls the flow of energy from the second energy storage element to the first energy storage element to regulate the voltage level of the energy stored in the first energy storage element.
摘要翻译：用于集成电路的电源具有第一和第二能量存储元件和调节器。第一能量存储元件存储用于应用于集成电路的能量。第二能量存储元件将能量存储在比由第一能量存储元件存储的能量更高的电压。调节器将能量存储元件互连并且控制从第二能量存储元件到第一能量存储元件的能量流，以调节存储在第一能量存储元件中的能量的电压电平。

6. 发明授权

US07317303B1 Rectified power supply 失效
标题翻译：整流电源
公开(公告)号：US07317303B1
公开(公告)日：2008-01-08
申请号：US11564954
申请日：2006-11-30
申请人： Alan D. DeVilbiss
发明人： Alan D. DeVilbiss
IPC分类号： G05F3/08 , H02M7/02
CPC分类号： G06K7/0008
摘要： A power supply creates a voltage difference between high and low power supply rails. The power supply has a voltage signal source, a capacitive coupling element, energy storage element 12, first and second rectifying diodes, a regulator, and bypass means for selectively decreasing the impedance between the voltage signal source and the low power supply rail or increasing the load presented to the voltage signal source. The capacitive coupling element is connected to the voltage signal source. Energy storage element 12 stores energy between the high and low power supply rails. The first rectifying diode is positioned between the capacitive coupling element and energy storage element 12. It is coupled to the voltage signal source through the capacitive coupling element and arranged to favor current flow toward energy storage element 12 from the capacitive coupling element. The second rectifying diode is positioned between the capacitive coupling element and the low power supply rail. It is coupled to the voltage signal source through the capacitive coupling element and arranged to favor current flow toward the capacitive coupling element from the low power supply rail. The regulator regulates the level of energy stored in energy storage element 12.
摘要翻译：电源在高电源和低电源轨之间产生电压差。电源具有电压信号源，电容耦合元件，能量存储元件12，第一和第二整流二极管，调节器和旁路装置，用于选择性地降低电压信号源和低电源轨之间的阻抗，或增加载入电压信号源。电容耦合元件连接到电压信号源。储能元件12在高电源轨和低电源轨之间存储能量。第一整流二极管位于电容耦合元件和能量存储元件12之间。它通过电容耦合元件耦合到电压信号源，并且被布置成有利于从电容耦合元件朝向能量存储元件12的电流流动。第二整流二极管位于电容耦合元件和低电源轨之间。其通过电容耦合元件耦合到电压信号源，并且被布置成有利于从低电源轨道朝向电容耦合元件的电流。调节器调节存储在储能元件12中的能量水平。

7. 发明授权

US07078304B2 Method for producing an electrical circuit 失效
标题翻译：电路制造方法
公开(公告)号：US07078304B2
公开(公告)日：2006-07-18
申请号：US11098738
申请日：2005-04-04
申请人： Gary F. Derbenwick , Alan D. DeVilbiss
发明人： Gary F. Derbenwick , Alan D. DeVilbiss
IPC分类号： H01L21/8222
CPC分类号： H05K1/186 , G06K19/07749 , H01L23/49833 , H01L2224/16 , H05K1/189 , H05K2201/055
摘要： An electrical circuit is formed by forming and patterning a conductive layer on a substrate, forming and patterning a conductive layer on another substrate, depositing a dielectric layer on at least a portion of one of conductive layers, mounting an integrated circuit (IC) between the substrates, coupling the IC to the conductive layers, and affixing the substrates together with the conductive layers between the substrates. These are either separate substrates or a unitary substrate. The IC is mounted either to a substrate, a conductive layer, or a dielectric layer. The IC is coupled to the conductive layers either directly or through openings formed in the dielectric layer. An interior conductive layer may be used to couple the IC to the conductive layers.
摘要翻译：通过在衬底上形成和图案化导电层形成电路，在另一个衬底上形成和构图导电层，在导电层的至少一部分上沉积介电层，将集成电路（IC）安装在衬底，将IC耦合到导电层，以及将衬底与导电层粘合在衬底之间。这些是单独的基底或单一基底。 IC安装在基板，导电层或电介质层上。 IC直接地或通过形成在电介质层中的开口耦合到导电层。内部导电层可以用于将IC耦合到导电层。

8. 发明授权

US06760246B1 Method of writing ferroelectric field effect transistor 失效
标题翻译：写入铁电场效应晶体管的方法
公开(公告)号：US06760246B1
公开(公告)日：2004-07-06
申请号：US10136210
申请日：2002-05-01
申请人： David A. Kamp , Alan D. DeVilbiss
发明人： David A. Kamp , Alan D. DeVilbiss
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A ferroelectric field effect transistor (FET) has a gate, source, drain, and substrate. A negative voltage is applied to the gate. Ground potential is applied to the source, drain, and substrate. The negative voltage has a magnitude at least equal to the coercive voltage of the FET. A positive voltage is then applied to the gate. Ground potential is applied to the source and substrate. The positive voltage is no less than the coercive voltage. Either a positive voltage or a ground potential is applied to the drain to write a logic state to the FET. A voltage is applied to the gate. Ground potential is applied to the source. A positive voltage is applied to the drain. The drain current is measured and compared to a compare current. The relative size of the drain current compared to the compare current is indicative of the stored logic state in the FET.
摘要翻译：铁电场效应晶体管（FET）具有栅极，源极，漏极和衬底。向栅极施加负电压。接地电位施加到源极，漏极和衬底。负电压的幅度至少等于FET的矫顽电压。然后将正电压施加到栅极。接地电位施加到源极和衬底上。正电压不小于矫顽电压。将正电压或接地电位施加到漏极，以将逻辑状态写入FET。电压被施加到门。接地电位被施加到源。向漏极施加正电压。测量漏极电流并将其与比较电流进行比较。与比较电流相比，漏极电流的相对大小表示FET中存储的逻辑状态。

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