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    • 1. 发明授权
    • Integrated inrush current limiter circuit and method
    • 集成涌流限流电路及方法
    • US07099135B2
    • 2006-08-29
    • US10287831
    • 2002-11-05
    • Alan BallDavid BriggsSuzanne NeeStephen Robb
    • Alan BallDavid BriggsSuzanne NeeStephen Robb
    • H02H3/00
    • H02H9/001H02H1/0007
    • An inrush current limiter circuit (20) includes a detection circuit (30) that produces a control signal (VDRIVE) from a sense current (ISENSE). A power transistor responds to the control signal and has a source (51) coupled to an input node (12) to receive a supply voltage (ground) and a drain (53) for routing a load current (ILOAD) to an output node (45) as a protection signal (VSW). A sense transistor responds to the control signal and has a source scaled to the source of the power transistor and coupled to the input node to route a portion of the load current to the output node as the sense current.
    • 浪涌电流限制器电路(20)包括检测电路(30),该检测电路从感测电流(I SENSE)产生控制信号(V SUB驱动)。 功率晶体管响应于控制信号并且具有耦合到输入节点(12)的源(51)以接收电源电压(接地)和用于布线负载电流(I LOAD)的漏极(53) SUB>)作为保护信号(V SW SW)输出到输出节点(45)。 感测晶体管响应于控制信号并且具有被缩放到功率晶体管的源并且耦合到输入节点的源,以将负载电流的一部分路由到输出节点作为感测电流。