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1. 发明授权

US08158498B2 P-channel MOS transistor and fabrication process thereof 有权
标题翻译： P沟道MOS晶体管及其制造工艺
公开(公告)号：US08158498B2
公开(公告)日：2012-04-17
申请号：US12379832
申请日：2009-03-03
申请人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L21/44
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.
摘要翻译： P沟道MOS晶体管包括通过栅极绝缘膜对应于其沟道区域在硅衬底上形成的栅电极，在其各个侧壁表面上承载侧壁绝缘膜的栅极电极以及p型沟道MOS晶体管的源极和漏极区域在侧壁绝缘膜的相应外侧的基板中形成，其中源极和漏极区域中的每一个围绕在其中积聚压缩应力的p型多晶体区域。

2. 发明授权

US07816766B2 Semiconductor device with compressive and tensile stresses 有权
标题翻译：具有压缩和拉伸应力的半导体器件
公开(公告)号：US07816766B2
公开(公告)日：2010-10-19
申请号：US11131211
申请日：2005-05-18
申请人： Naoyoshi Tamura , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Masashi Shima
发明人： Naoyoshi Tamura , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Masashi Shima
IPC分类号： H01L29/06
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films epitaxially to the silicon substrate so as to be enclosed respectively by the source and drain regions, each of the SiGe mixed crystal regions being grown to a level above a level of a gate insulation film interface between the gate insulation film and the silicon substrate, wherein there is provided a compressive stress film at respective top surfaces of the SiGe mixed crystal regions.
摘要翻译：半导体器件包括形成在硅衬底上的栅电极，其对应于通过栅极绝缘膜的沟道区，以及在栅极上的侧壁绝缘膜的相应外侧在硅衬底中形成的p型源区和漏区，一对SiGe混合晶体区域，其形成在硅衬底的外侧的侧壁绝缘膜的外侧的硅衬底上，以分别由源极和漏极区域包围，每个SiGe混合晶体区域生长到在栅极绝缘膜和硅衬底之间的栅极绝缘膜界面的电平以上的水平面，其中在SiGe混合晶体区域的各个顶表面处提供压应力膜。

3. 发明授权

US07791064B2 Semiconductor device and fabrication method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07791064B2
公开(公告)日：2010-09-07
申请号：US11107945
申请日：2005-04-18
申请人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
发明人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/30608 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/4975 , H01L29/518 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
摘要翻译：一种半导体器件包括：栅极电极，形成在硅衬底上，栅极绝缘膜对应于沟道区，形成在硅衬底中的p型扩散区的源极和漏极区域的侧壁绝缘膜的相应外侧栅电极和在硅衬底中在与硅衬底呈外延角的侧壁绝缘膜的各外侧形成的一对SiGe混合晶体区域，SiGe混晶区域由彼此相对的侧壁表面限定，其中在每个SiGe混合晶体区域中，侧壁表面由相对于硅衬底的主表面形成相应不同角度的多个面限定。

4. 发明申请

US20090176343A1 P-channel MOS transistor and fabrication process thereof 有权
公开(公告)号：US20090176343A1
公开(公告)日：2009-07-09
申请号：US12379832
申请日：2009-03-03
申请人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L21/336
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.

5. 发明授权

US07518188B2 P-channel MOS transistor and fabrication process thereof 有权
标题翻译： P沟道MOS晶体管及其制造工艺
公开(公告)号：US07518188B2
公开(公告)日：2009-04-14
申请号：US11180791
申请日：2005-07-14
申请人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L29/76
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.
摘要翻译： P沟道MOS晶体管包括通过栅极绝缘膜对应于其沟道区域在硅衬底上形成的栅电极，在其各个侧壁表面上承载侧壁绝缘膜的栅极电极以及p型沟道MOS晶体管的源极和漏极区域在侧壁绝缘膜的相应外侧的基板中形成，其中源极和漏极区域中的每一个围绕在其中积聚压缩应力的p型多晶体区域。

6. 发明授权

US07476941B2 Semiconductor integrated circuit device and fabrication process thereof 有权
标题翻译：半导体集成电路器件及其制造工艺
公开(公告)号：US07476941B2
公开(公告)日：2009-01-13
申请号：US11712418
申请日：2007-03-01
申请人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L23/62
CPC分类号： H01L29/41758 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/045 , H01L29/4933 , H01L29/66507 , H01L29/66636 , H01L29/7842 , H01L29/7843 , H01L29/7848
摘要： A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.
摘要翻译：半导体集成电路包括分别形成在衬底的第一和第二器件区域中的n沟道MOS晶体管和p沟道MOS晶体管，所述n沟道MOS晶体管包括在其各个侧壁表面上承载侧壁绝缘膜的第一栅极电极所述p沟道MOS晶体管包括在其各个侧壁表面上承载侧壁绝缘膜的第二栅电极，其中在所述第一和第二器件区上的所述衬底上设置有应力膜，使得所述应力器膜覆盖所述第一栅电极，包括其侧壁绝缘膜和包括其侧壁绝缘膜的第二栅电极，其中至少在第二栅电极的基部附近，应力膜在第二器件区域中具有降低的膜厚度。

7. 发明授权

US07262465B2 P-channel MOS transistor and fabrication process thereof 有权
标题翻译： P沟道MOS晶体管及其制造工艺
公开(公告)号：US07262465B2
公开(公告)日：2007-08-28
申请号：US11114047
申请日：2005-04-26
申请人： Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura , Yosuke Shimamune , Masashi Shima
发明人： Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura , Yosuke Shimamune , Masashi Shima
IPC分类号： H01L27/01
CPC分类号： H01L29/78639 , H01L29/7842 , H01L29/7848 , H01L29/78684
摘要： A p-channel MOS transistor includes a strained SOI substrate formed of a SiGe mixed crystal layer and a strained Si layer formed on the SiGe mixed crystal layer via an insulation film, a channel region being formed in the strained Si layer, a gate electrode formed on the strained Si layer in correspondence to the channel region via a gate insulation film, and first and second p-type diffusion regions formed in the strained Si layer at respective first and second sides of the channel region, wherein the strained Si layer has first and second sidewall surfaces respectively at the first and second sides thereof, a first SiGe mixed crystal region being formed epitaxially to the SiGe mixed crystal layer in contact with the first sidewall surface, a second SiGe mixed crystal region being formed epitaxially to the SiGe mixed crystal layer in contact with the second sidewall surface, the first and second SiGe mixed crystal regions being in lattice matching with the strained silicon layer respectively at the first and second sidewall surfaces.
摘要翻译： p沟道MOS晶体管包括由SiGe混晶层形成的应变SOI衬底和经由绝缘膜形成在SiGe混晶层上的应变Si层，形成在应变Si层中的沟道区，形成栅电极在通过栅极绝缘膜对应于沟道区的应变Si层上，以及在沟道区的相应第一和第二侧处在应变Si层中形成的第一和第二p型扩散区，其中应变Si层具有第一和第二侧壁表面，分别与第一侧壁表面接触的SiGe混合晶体层外延形成第一SiGe混合晶体区域，第二SiGe混合晶体区域外延形成SiGe混合晶体层与第二侧壁表面接触，第一和第二SiGe混合晶体区域与应变硅层的格子匹配在第一和第二侧壁表面上。

8. 发明申请

US20070148835A1 Semiconductor integrated circuit device and fabrication process thereof 有权
公开(公告)号：US20070148835A1
公开(公告)日：2007-06-28
申请号：US11712418
申请日：2007-03-01
申请人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L21/84
CPC分类号： H01L29/41758 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/045 , H01L29/4933 , H01L29/66507 , H01L29/66636 , H01L29/7842 , H01L29/7843 , H01L29/7848
摘要： A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.

9. 发明申请

US20060202280A1 P-channel MOS transistor and fabrication process thereof 有权
公开(公告)号：US20060202280A1
公开(公告)日：2006-09-14
申请号：US11180791
申请日：2005-07-14
申请人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
发明人： Masashi Shima , Yosuke Shimamune , Akiyoshi Hatada , Akira Katakami , Naoyoshi Tamura
IPC分类号： H01L29/76
CPC分类号： H01L29/165 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.

10. 发明申请

US20130248930A1 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
公开(公告)号：US20130248930A1
公开(公告)日：2013-09-26
申请号：US13894871
申请日：2013-05-15
申请人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
发明人： Yosuke Shimamune , Akira Katakami , Akiyoshi Hatada , Masashi Shima , Naoyoshi Tamura
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/02381 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L21/02639 , H01L21/28518 , H01L21/30608 , H01L29/045 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/4975 , H01L29/518 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7833 , Y10S257/90
摘要： A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.

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