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    • 9. 发明授权
    • System of transferring data in a multi-CPU arrangement using address
generators
    • 使用地址生成器在多CPU布置中传输数据的系统
    • US5341473A
    • 1994-08-23
    • US743052
    • 1991-08-09
    • Michio Takayama
    • Michio Takayama
    • G06F13/28G06F9/46G06F13/42
    • G06F13/28
    • A system for transferring digital signals between at least two printed circuit boards (packages) provided within a digital signal processing apparatus and each mounting a plurality of electronic parts such as microprocessors between a CPU package and a peripheral control package. The CPU package has a microprocessor (CPU), a transmitting sequential address generator 1, a receiving sequential address generator circuit 1, a transmitting dual port RAM 1 and a receiving dual port RAM 1. The peripheral control package has a digital processing circuit, a transmitting sequential address generator 2, a receiving sequential address generator 2, a transmitting dual port RAM 2 and a receiving dual port RAM. When a control information is to be sent from the CPU to the digital processing circuit, the CPU is required to only write the control information in the transmitting dual port RAM. The control information is read out from the transmitting dual port RAM according to sequential addresses produced by the transmitting sequential address generator independently from the CPU and outputted to the receiving dual port RAM of the peripheral control package. The control information thus outputted is written in the receiving dual port RAM 2 according to addresses produced by the receiving sequential address generator 2. The digital processing circuit reads the control information from the receiving dual port RAM 2 and processes it in a manner predetermined. This is the same for a case where information is transferred from the digital processing circuit to the CPU.
    • 一种用于在设置在数字信号处理装置内的至少两个印刷电路板(封装)之间传送数字信号的系统,并且每个在CPU封装和外围控制封装之间安装多个电子部件,例如微处理器。 CPU封装具有微处理器(CPU),发送顺序地址发生器1,接收顺序地址发生器电路1,发送双端口RAM 1和接收双端口RAM 1.外围控制包具有数字处理电路, 发送顺序地址生成器2,接收顺序地址生成器2,发送双端口RAM2和接收双端口RAM。 当控制信息从CPU发送到数字处理电路时,CPU只需要在发送双端口RAM中写入控制信息。 控制信息根据由发送顺序地址发生器产生的连续地址从发送双端口RAM中读出,并独立于CPU并输出到外围控制包的接收双端口RAM。 这样输出的控制信息根据由接收顺序地址发生器2产生的地址写入接收双端口RAM2中。数字处理电路从接收双端口RAM2读取控制信息,并以预定的方式对其进行处理。 对于从数字处理电路向CPU传送信息的情况,这是相同的。