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    • 6. 发明授权
    • Serial to parallel data converting circuit
    • 串行到并行数据转换电路
    • US5426784A
    • 1995-06-20
    • US16532
    • 1993-02-11
    • Atsumi KawataHirotoshi TanakaHiroki YamashitaKenji NagaiMinoru YamadaNobuhiro Taniguchi
    • Atsumi KawataHirotoshi TanakaHiroki YamashitaKenji NagaiMinoru YamadaNobuhiro Taniguchi
    • G06F5/00H03M9/00G06F1/04
    • H03M9/00
    • A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.
    • 移位寄存器10接收串行数据并且与所接收的串行数据的定时同步地输出并行数据。 移位寄存器组20,21从移位寄存器10接收并行数据的位输出。移位寄存器组中的移位寄存器20,21的位数被设定在对应于并行的位输出的一定条件 提供了多个符合电路107,108,其检测预设数据起始模式与移位寄存器组中的数据的位排列之间的一致性。 选择器306根据来自符合电路107,108的输出信号从移位寄存器组中选择一组并行输出。因此,只有移位寄存器10在与所接收的串行数据相同的定时进行高速操作,以及 其他电路以较慢的速度工作,其定时比接收的串行数据的时间长几倍,从而消除复杂的时序并避免难度控制逻辑。