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1. 发明申请

US20090187903A1 VIRTUAL MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：虚拟多媒体系统
公开(公告)号：US20090187903A1
公开(公告)日：2009-07-23
申请号：US12346987
申请日：2008-12-31
申请人： Akira UEDA , Takao YAMAMOTO , Shinji OZAKI , Masahide KAKEDA
发明人： Akira UEDA , Takao YAMAMOTO , Shinji OZAKI , Masahide KAKEDA
IPC分类号： G06F9/455
CPC分类号： G06F9/45558 , G06F11/3636 , G06F11/3648 , G06F2009/45591
摘要： A virtual multiprocessor system which does not require a memory apparatus for debugging includes: a physical processor, storage units for storing status information indicating respective statuses of logic processors, a dispatch unit which assigns one of the logic processors by switching the logic processors with respect to a physical processor, and an interrupt unit which suspends the processing currently executed by a current logic processor among the logic processors by issuing a debug interrupt request to the current logic processor; in the virtual multiprocessor system, the dispatch unit stores status information corresponding to the current logic processor into one of the storage units in response to the debug interrupt request issued to the current logic processor that is assigned to the physical processor.
摘要翻译：不需要用于调试的存储器装置的虚拟多处理器系统包括：物理处理器，用于存储指示逻辑处理器的各自状态的状态信息的存储单元，调度单元，其通过将逻辑处理器相对于物理处理器和中断单元，其通过向当前逻辑处理器发出调试中断请求来暂停当前逻辑处理器在逻辑处理器中执行的处理; 在虚拟多处理器系统中，调度单元响应于发送给分配给物理处理器的当前逻辑处理器的调试中断请求，将与当前逻辑处理器相对应的状态信息存储到一个存储单元中。

2. 发明申请

US20120023311A1 PROCESSOR APPARATUS AND MULTITHREAD PROCESSOR APPARATUS 有权
标题翻译：加工设备和多用途加工设备
公开(公告)号：US20120023311A1
公开(公告)日：2012-01-26
申请号：US13215623
申请日：2011-08-23
申请人： Takao YAMAMOTO , Shinji OZAKI , Masahide KAKEDA , Masaitsu NAKAJIMA
发明人： Takao YAMAMOTO , Shinji OZAKI , Masahide KAKEDA , Masaitsu NAKAJIMA
IPC分类号： G06F9/48 , G06F9/40
CPC分类号： G06F9/462 , G06F9/30101 , G06F9/30123 , G06F9/3851 , G06F9/3885
摘要： A processor apparatus according to the present invention is a processor apparatus which shares hardware resources between a plurality of processors, and includes: a first determination unit which determines whether or not a register in each of the hardware resources holds extension context data of a program that is currently executed; a second determination unit which determines to which processor the extension context data in the hardware resource corresponds; a first transfer unit which saves and restores the extension context data between programs in the processor; and a second transfer unit which saves and restores the extension context data between programs between different processors.
摘要翻译：根据本发明的处理器装置是在多个处理器之间共享硬件资源的处理器装置，包括：第一确定单元，确定每个硬件资源中的寄存器是否保存有程序的扩展上下文数据，目前执行; 第二确定单元，确定硬件资源中的扩展上下文数据对哪个处理器; 第一传送单元，其在所述处理器中的节目之间保存和恢复所述扩展上下文数据; 以及第二传送单元，其在不同处理器之间的节目之间保存和恢复扩展上下文数据。

3. 发明申请

US20120008674A1 MULTITHREAD PROCESSOR AND DIGITAL TELEVISION SYSTEM 审中-公开
标题翻译：多功能处理器和数字电视系统
公开(公告)号：US20120008674A1
公开(公告)日：2012-01-12
申请号：US13209804
申请日：2011-08-15
申请人： Takao YAMAMOTO , Shinji OZAKI , Masahide KAKEDA , Masaitsu NAKAJIMA
发明人： Takao YAMAMOTO , Shinji OZAKI , Masahide KAKEDA , Masaitsu NAKAJIMA
IPC分类号： H04N11/02 , G06F12/10
CPC分类号： G06F9/52 , G06F12/1027
摘要： A multithread processor including: an execution unit including a physical processor; and a translation lookaside buffer (TLB) which converts, to a physical address, a logical address output from the execution unit, and logical processors are implemented on the physical processor, a first logical processor that is a part of the logical processors constitutes a first subsystem having a first virtual space, a second logical processor that is a part of the logical processors and different from the first logical processor constitutes a second subsystem having a second virtual space, each of the first and the second subsystems has processes to be assigned to the logical processors, and the logical address includes: a first TLB access virtual identifier for identifying one of the first and the second subsystems; and a process identifier for identifying a corresponding one of the processes in each of the first and the second subsystems.
摘要翻译：一种多线程处理器，包括：包括物理处理器的执行单元; 以及翻译后备缓冲器（TLB），其将物理地址转换为从执行单元输出的逻辑地址，并且在物理处理器上实现逻辑处理器，作为逻辑处理器的一部分的第一逻辑处理器构成第一具有第一虚拟空间的子系统，作为逻辑处理器的一部分并且不同于第一逻辑处理器的第二逻辑处理器构成具有第二虚拟空间的第二子系统，第一和第二子系统中的每一个具有被分配给逻辑处理器和逻辑地址包括：用于识别第一和第二子系统之一的第一TLB访问虚拟标识符; 以及用于识别第一和第二子系统中的每一个中的相应一个处理的进程标识符。

4. 发明申请

US20090113179A1 OPERATIONAL PROCESSING APPARATUS, PROCESSOR, PROGRAM CONVERTING APPARATUS AND PROGRAM 审中-公开
标题翻译：操作处理装置，处理器，程序转换装置和程序
公开(公告)号：US20090113179A1
公开(公告)日：2009-04-30
申请号：US12259589
申请日：2008-10-28
申请人： Masahide KAKEDA , Shinji OZAKI , Takao YAMAMOTO
发明人： Masahide KAKEDA , Shinji OZAKI , Takao YAMAMOTO
IPC分类号： G06F9/312
CPC分类号： G06F9/3885 , G06F9/30087 , G06F9/30167 , G06F9/3851 , G06F9/3853
摘要： The present invention provides an operational processing apparatus which can guarantee a period for executing instructions in the shortest cycle when the operational processing apparatus synchronizes with a hardware accelerator. A processor in the present invention simultaneously issues and executes instructions including instruction groups having a simultaneously issueable instruction. The processor executes a program including a specific instruction. The specific instruction instructs to exclude an instruction subsequent to the specific instruction out of the instruction groups including the specific instruction, and to suspend issuing the instruction subsequent to the specific instruction only during a predetermined period immediately after the specific instruction is issued.
摘要翻译：本发明提供了一种操作处理装置，当操作处理装置与硬件加速器同步时，可以保证在最短周期内执行指令的周期。本发明的处理器同时发出并执行包括具有同时可发出指令的指令组的指令。处理器执行包括特定指令的程序。特定指令指示从包括特定指令的指令组中排除特定指令之后的指令，并且仅在特定指令发出之后的预定时段内暂停发出特定指令之后的指令。

5. 发明申请

US20080109809A1 MULTITHREADED PROCESSOR 有权
标题翻译：多功能处理器
公开(公告)号：US20080109809A1
公开(公告)日：2008-05-08
申请号：US11936296
申请日：2007-11-07
申请人： Hiroyuki MORISHITA , Shinji OZAKI , Takao YAMAMOTO , Masaitsu NAKAJIMA
发明人： Hiroyuki MORISHITA , Shinji OZAKI , Takao YAMAMOTO , Masaitsu NAKAJIMA
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： Provided is a multithreaded processor that can accurately estimate processing time necessary for each thread, and a multithreaded processor that simultaneously executes instruction streams, the multithreaded processor including: a computing unit group that executes instructions; an instruction scheduler that groups the instructions into groups for each of the instruction streams, the instructions being included in the each of instruction streams, and each of the groups being made up of instructions among the instructions to be simultaneously issued to the computing units; an instruction buffer which holds the instructions for each of the groups grouped by the instruction scheduler, the instructions being included in the each of instruction streams; and an issued instruction determining unit that reads the instructions for each of the groups from the instruction buffer in each of execution cycles of the multithreaded processor, and that issues the read instructions to the computing unit group.
摘要翻译：提供了一种可以准确地估计每个线程所需的处理时间的多线程处理器，以及同时执行指令流的多线程处理器，所述多线程处理器包括：执行指令的计算单元组; 指令调度器，其将指令分组为每个指令流，每个指令流中包括指令，并且每个组由指令同时发出到计算单元; 指令缓冲器，其保存由指令调度器分组的每个组的指令，所述指令被包括在每个指令流中; 以及发出指令确定单元，其在多线程处理器的每个执行周期中从指令缓冲器读取每个组的指令，并将读取指令发布到计算单元组。

6. 发明申请

US20080276044A1 PROCESSING APPARATUS 审中-公开
标题翻译：加工设备
公开(公告)号：US20080276044A1
公开(公告)日：2008-11-06
申请号：US12139059
申请日：2008-06-13
申请人： Shinji OZAKI
发明人： Shinji OZAKI
IPC分类号： G06F12/08
CPC分类号： G06F9/3802 , G06F1/3203 , G06F1/3275 , G06F9/30101 , G06F9/30189 , G06F9/3836 , G06F9/3842 , G06F9/3869 , G06F12/0864 , G06F2212/1028 , G06F2212/6082 , Y02D10/13 , Y02D10/14
摘要： A processing apparatus which executes a program and performs processes of the program, includes an execution circuit including a plurality of central processing units, each having a respective cache memory, and each of the respective cache memories has an N-way set-associative structure with N-ways in which one line is made up of plural words. Each of the respective cache memories includes a data memory array which is simultaneously read-out in multiple-word-widths, and can be read-out using one of a type one read-out and a type two read-out. In the type one read-out, plural words in the same word positions within respective lines are simultaneously read-out from corresponding lines belonging to different ways, and in the type two read out, plural words making up one line of one way are simultaneously read-out. The cache memory has a first read-out mode and a second read-out mode. In the first read-out mode, a word belonging to a way which is hit by a memory access is selected from among the plural words read-out using the type-one read out, and the selected word is outputted, and in the second read-out mode, plural words are read-out from a way which is hit, using the type-two read out, and read-out plural words are outputted.
摘要翻译：执行程序并执行程序的处理的处理装置包括执行电路，该执行电路包括多个中央处理单元，每个中央处理单元具有各自的高速缓冲存储器，并且每个高速缓存存储器具有N路组合关联结构，一行由多个单词构成的N方式。各个高速缓存存储器中的每一个包括以多个字宽同时读出的数据存储器阵列，并且可以使用类型1读出和类型2读出之一来读出。在一类读出中，各行中的相同字位置中的多个字同时从属于不同方式的相应行同时读出，并且在类型2读出中，组合一行一行的多个单词同时读出。高速缓冲存储器具有第一读出模式和第二读出模式。在第一读出模式中，从读出的类型1中读出的多个单词中选择属于存储器访问方式的单词，并输出所选择的单词，并且在第二读取模式中，读出模式，通过使用类型2读出，从被击中的方式读出多个字，并且读出多个字被输出。

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