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1. 发明申请

US20120319338A1 COVER MEMBER AND SUSPENSION 有权
标题翻译：盖会员和暂停
公开(公告)号：US20120319338A1
公开(公告)日：2012-12-20
申请号：US13324697
申请日：2011-12-13
申请人： Akira Takada , Shinichi Sutou
发明人： Akira Takada , Shinichi Sutou
IPC分类号： B60G15/06 , F16F13/00 , B32B3/30
CPC分类号： F16F9/38
摘要： A cover member having plural peak portions and plural trough portions, and freely stretched and shrunk in an array direction of the plural peak portions and the plural trough portions or freely bent, the cover member includes: a hollow part formed in each of the plural peak portions, the hollow part being hollowed toward an inner side from a peak of each of the plural peak portions, being formed in a circumferential direction, and having edge parts, a bottom part and side parts located between the edge parts and the bottom part. The edge parts of the hollow part are brought into contact with each other before the side parts of the hollow part are brought into contact with each other, when at least one of the plural peak portions is subjected to force in a direction intersecting with the array direction from an outside.
摘要翻译：一种盖构件，具有多个峰部和多个谷部，并且在所述多个峰部和所述多个谷部的排列方向上自由伸缩并自由弯曲，所述盖构件包括：形成在所述多个峰所述中空部从所述多个峰部中的每一个峰的内侧向内侧中空化，沿圆周方向形成，并且具有边缘部，底部和位于所述边缘部和所述底部之间的侧部。当中空部分的边缘部分彼此接触时，中空部分的边缘部分彼此接触，当多个峰部中的至少一个在与阵列相交的方向上施加力时方向从外面。

2. 发明授权

US08657270B2 Cover member and suspension 有权
标题翻译：封面和悬挂
公开(公告)号：US08657270B2
公开(公告)日：2014-02-25
申请号：US13324697
申请日：2011-12-13
申请人： Akira Takada , Shinichi Sutou
发明人： Akira Takada , Shinichi Sutou
IPC分类号： F16F9/38
CPC分类号： F16F9/38
摘要： A cover member having plural peak portions and plural trough portions, and freely stretched and shrunk in an array direction of the plural peak portions and the plural trough portions or freely bent, the cover member includes: a hollow part formed in each of the plural peak portions, the hollow part being hollowed toward an inner side from a peak of each of the plural peak portions, being formed in a circumferential direction, and having edge parts, a bottom part and side parts located between the edge parts and the bottom part. The edge parts of the hollow part are brought into contact with each other before the side parts of the hollow part are brought into contact with each other, when at least one of the plural peak portions is subjected to force in a direction intersecting with the array direction from an outside.
摘要翻译：一种盖构件，具有多个峰部和多个谷部，并且在所述多个峰部和所述多个谷部的排列方向上自由伸缩并自由弯曲，所述盖构件包括：形成在所述多个峰所述中空部从所述多个峰部中的每一个峰的内侧向内侧中空化，沿圆周方向形成，并且具有边缘部，底部和位于所述边缘部和所述底部之间的侧部。当中空部分的边缘部分彼此接触时，中空部分的边缘部分彼此接触，当多个峰部中的至少一个在与阵列相交的方向上施加力时方向从外面。

3. 发明授权

US09251117B2 Reconfigurable circuit with suspension control circuit 有权
标题翻译：具有悬架控制电路的可重构电路
公开(公告)号：US09251117B2
公开(公告)日：2016-02-02
申请号：US12723320
申请日：2010-03-12
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F9/30 , G06F15/78 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3897
摘要： A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.
摘要翻译：可重构电路包括可重配算术执行单元阵列，其包括多个算术执行单元和网络电路，以在算术执行单元之间提供可重新配置的连接;悬架控制电路，被配置为控制可重构算术执行单元阵列的操作的暂停和恢复以及缓冲电路，被配置为在暂停所述可重构算术执行单元阵列的操作时临时存储从外部源提供的数据，并且在恢复所述可重构算术执行的操作时将所存储的数据提供给所述可重新配置的算术执行单元阵列单位阵列

4. 发明申请

US20100257335A1 RECONFIGURABLE CIRCUIT WITH SUSPENSION CONTROL CIRCUIT 有权
标题翻译：具有悬挂控制电路的可重新连接电路
公开(公告)号：US20100257335A1
公开(公告)日：2010-10-07
申请号：US12723320
申请日：2010-03-12
申请人： Takashi Hanai , Shinichi Sutou
发明人： Takashi Hanai , Shinichi Sutou
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F15/7867 , G06F9/3897
摘要： A reconfigurable circuit includes a reconfigurable arithmetic execution unit array including a plurality of arithmetic execution units and a network circuit to provide reconfigurable connections between the arithmetic execution units, a suspension control circuit configured to control suspension and resumption of operation of the reconfigurable arithmetic execution unit array, and a buffer circuit configured to temporarily store data supplied from an external source upon suspension of the operation of the reconfigurable arithmetic execution unit array and to supply the stored data to the reconfigurable arithmetic execution unit array upon resumption of the operation of the reconfigurable arithmetic execution unit array.
摘要翻译：可重构电路包括可重配算术执行单元阵列，其包括多个算术执行单元和网络电路，以在算术执行单元之间提供可重新配置的连接;悬架控制电路，被配置为控制可重构算术执行单元阵列的操作的暂停和恢复以及缓冲电路，被配置为在暂停所述可重构算术执行单元阵列的操作时临时存储从外部源提供的数据，并且在恢复所述可重构算术执行的操作时将所存储的数据提供给所述可重新配置的算术执行单元阵列单位阵列

5. 发明授权

US08539415B2 Reconfigurable circuit, its design method, and design apparatus 有权
标题翻译：可重构电路，其设计方法和设计装置
公开(公告)号：US08539415B2
公开(公告)日：2013-09-17
申请号：US12635347
申请日：2009-12-10
申请人： Shinichi Sutou
发明人： Shinichi Sutou
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F15/7867 , G06F17/5045
摘要： A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration.
摘要翻译：可重构电路设计方法包括：输入步骤，输入包括执行处理的多个处理器元件的可重构电路的默认配置的设计数据;以及第一生成步骤，生成通过修改至少一个处理器元件而获得的设计数据可重配置电路具有默认配置。

6. 发明授权

US08291360B2 Data conversion apparatus, method, and computer-readable recording medium storing program for generating circuit configuration information from circuit description 有权
标题翻译：数据转换装置，方法以及用于从电路描述产生电路配置信息的计算机可读记录介质存储程序
公开(公告)号：US08291360B2
公开(公告)日：2012-10-16
申请号：US12503455
申请日：2009-07-15
申请人： Hayato Higuchi , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
发明人： Hayato Higuchi , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.
摘要翻译：一种用于将与动态可重构电路有关的电路描述转换为电路配置信息的数据转换装置，所述数据转换装置包括从电路描述生成数据流图的第一生成部分; 段计数确定部分，确定用于分割由第一代部分生成的数据流图的段数; 虚拟电路创建部分，其创建虚拟电路，所述虚拟电路具有与所述段计数确定部确定的所述资源的数量相乘的所述动态可重配置电路的资源数量; 第二代部分，从电路描述生成与由虚拟电路创建部分创建的虚拟电路对应的数据流图; 以及根据数据流图分配和调整虚拟电路的资源的转换部分。

7. 发明授权

US5781560A System testing device and method using JTAG circuit for testing high-package density printed circuit boards 失效
标题翻译：使用JTAG电路测试高封装密度印刷电路板的系统测试装置和方法
公开(公告)号：US5781560A
公开(公告)日：1998-07-14
申请号：US902950
申请日：1997-07-30
申请人： Kayoko Kawano , Yasushi Takaki , Shinichi Sutou , Kazuhiro Hara
发明人： Kayoko Kawano , Yasushi Takaki , Shinichi Sutou , Kazuhiro Hara
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , G06F11/273
CPC分类号： G06F11/2736 , G01R31/318536
摘要： A method and system testing device for testing a printed circuit board includes a JTAG circuit provided with a JTAG instruction storage unit for storing a command to control a system logic circuit; and a JTAG data storage unit for storing data used to control the system logic circuit. The system testing device tests the system logic circuit in an LSI by selectively inputting/outputting data to a boundary scan register, a bypass register, the JTAG instruction storage unit, and the JTAG data storage unit.
摘要翻译：一种用于测试印刷电路板的方法和系统测试装置包括一个JTAG电路，该JTAG电路设有用于存储控制系统逻辑电路的命令的JTAG指令存储单元; 以及用于存储用于控制系统逻辑电路的数据的JTAG数据存储单元。系统测试装置通过选择性地向边界扫描寄存器，旁路寄存器，JTAG指令存储单元和JTAG数据存储单元输入/输出数据来测试LSI中的系统逻辑电路。

8. 发明授权

US09720879B2 Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit 有权
公开(公告)号：US09720879B2
公开(公告)日：2017-08-01
申请号：US12973730
申请日：2010-12-20
申请人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
发明人： Shinichi Sutou , Ichiro Kasama , Kyoji Sato , Takashi Hanai , Kiyomitsu Katou , Takahiro Kubota , Junji Sahoda
IPC分类号： G06F15/76 , G06F15/78 , G06F9/30 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3012 , G06F9/30141 , G06F9/3877
摘要： A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

9. 发明申请

US20100017761A1 DATA CONVERSION APPARATUS, DATA CONVERSION METHOD, AND COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAM 有权
标题翻译：数据转换装置，数据转换方法和计算机可读记录媒体存储程序
公开(公告)号：US20100017761A1
公开(公告)日：2010-01-21
申请号：US12503455
申请日：2009-07-15
申请人： Hayato HIGUCHI , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
发明人： Hayato HIGUCHI , Shinichi Sutou , Tsuguchika Tabaru , Manabu Matsuyama , Ryuichi Ohzeki , Toshihiro Suzuki
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.
摘要翻译：一种用于将与动态可重构电路有关的电路描述转换为电路配置信息的数据转换装置，所述数据转换装置包括从电路描述生成数据流图的第一生成部分; 段计数确定部分，确定用于分割由第一代部分生成的数据流图的段数; 虚拟电路创建部分，其创建虚拟电路，所述虚拟电路具有与所述段计数确定部确定的所述资源的数量相乘的所述动态可重配置电路的资源数量; 第二代部分，从电路描述生成与由虚拟电路创建部分创建的虚拟电路对应的数据流图; 以及根据数据流图分配和调整虚拟电路的资源的转换部分。

10. 发明申请

US20090319762A1 DYNAMIC RECONFIGURABLE CIRCUIT AND DATA TRANSMISSION CONTROL METHOD 有权
标题翻译：动态可重构电路和数据传输控制方法
公开(公告)号：US20090319762A1
公开(公告)日：2009-12-24
申请号：US12394863
申请日：2009-02-27
申请人： Takashi HANAI , Shinichi Sutou
发明人： Takashi HANAI , Shinichi Sutou
IPC分类号： G06F9/06
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3879 , G06F9/3891 , G06F9/3897 , G06F15/7867
摘要： A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.
摘要翻译：动态可重构电路包括多个簇，每个簇包括一组可重构处理元件。动态可重构电路能够根据包括处理元件的处理描述和处理元件之间的连接的上下文来动态地改变簇的配置。簇中的第一簇包括信号发生电路，当接收到改变上下文的指令时，产生指示改变上下文的指令的报告信号; 信号添加电路，其将由所述信号发生电路生成的所述报告信号与从所述第一簇发送到第二簇的输出数据相加; 以及数据清除电路，当接收到添加了由第二群集生成的报告信号的输出数据时，执行清除所接收的输出数据的清除处理。

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