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    • 8. 发明授权
    • Watch dog timer
    • 看狗定时器
    • US5542051A
    • 1996-07-30
    • US202247
    • 1994-02-25
    • Mitsuru SugitaYurika Sumida
    • Mitsuru SugitaYurika Sumida
    • G06F11/30G06F11/00G06F11/34G11B27/00
    • G06F11/0757
    • A watch don timer comprising a reload register 2 and a shift register 3 is disclosed. In the case where an object to be monitored is operating normally, a circuit 43 is supplied with as a reload request signal the rising timing of a monitor signal changing cyclically, which is reloaded from the reload register 2 of the shift, register 3 in synchronism with a reload request signal in accordance with the value of data located in each bit of the shift register 3. Circuits 41, 42 are adapted to detect an abnormal condition in the case where a reload request signal is given in a cycle shorter or longer than a predetermined cycle of reloading. This configuration realizes a watch dog timer with a comparatively small scale of circuit configuration in which the pulse width of the input signal is monitored, the cycle detected and the execution of a plurality of instructions monitored, while at the same time having a programmable width and cycle and a tolerable range thereof.
    • 公开了一种包括重载寄存器2和移位寄存器3的监视定时器。 在要监视的对象正常工作的情况下,电路43作为重新加载请求信号被提供,周期地改变监视信号的上升定时,其从移位寄存器3的重载寄存器2同步重新加载 具有根据位于移位寄存器3的每个位中的数据的值的重新加载请求信号。电路41,42适于在以更短或更长的周期中给出重新加载请求信号的情况下检测异常状况 预定的重新加载循环。 该配置实现了具有比较小规模的电路配置的看门狗定时器,其中监视输入信号的脉冲宽度,检测周期和监视多个指令的执行,同时具有可编程宽度和 循环和其可容许的范围。
    • 9. 发明授权
    • Multiprocessor-type one-chip microcomputer with dual-mode functional
terminals
    • 具有双模功能端子的多处理器型单片机
    • US5506994A
    • 1996-04-09
    • US49720
    • 1993-04-20
    • Mitsuru Sugita
    • Mitsuru Sugita
    • G06F15/167G06F15/78G06F13/00G06F15/16
    • G06F15/7814
    • A multiprocessor-type one-chip microcomputer, of the type having a plurality of processors, each having a separate address space, a plurality of programmable ROMs, for storing program data for each processor, and a set of functional terminals, with the microcomputer including a common writing bus and a control means for coupling either the common writing bus or a set of functional lines to the functional terminals based on the setting of a mode setting signal. During normal operations the functional lines are coupled to the functional terminals and each programmable ROM is accessed by a processor using addresses in the address space of the processor. When new instruction data is to be written to the programmable ROMs, the common writing bus is coupled to the functional terminals and instruction data is written to the programmable ROMs using addresses in a common address space.
    • 一种具有多个处理器的类型的多处理器型单片机,每个具有单独的地址空间,用于存储每个处理器的程序数据的多个可编程ROM和一组功能终端,其中微型计算机包括 公共写入总线和用于根据模式设置信号的设置将公共写入总线或一组功能线耦合到功能终端的控制装置。 在正常操作期间,功能线耦合到功能端子,并且处理器使用处理器的地址空间中的地址来访问每个可编程ROM。 当新的指令数据要写入可编程ROM时,公共写入总线与功能端子耦合,并且使用公共地址空间中的地址将指令数据写入可编程ROM。
    • 10. 发明授权
    • Dual port memory
    • 双端口内存
    • US5276842A
    • 1994-01-04
    • US682826
    • 1991-04-09
    • Mitsuru Sugita
    • Mitsuru Sugita
    • G11C11/41G06F13/16G06F15/167G06F12/00G06F13/00
    • G06F15/167G06F13/1663
    • A dual port memory 50 comprises two decoders 9a, 9b, and two sense amplifiers 14a, 14b, associated with a memory cell array 100. The dual port memory 50 can be accessed by a CPU 6 of the A system side and a CPU 7 of the B system side simultaneously. The occurrence of contention between the accesses of CPUs 6 and 7 with respect to the same memory cell is detected by an access contention detecting circuit 51. In response to contention detection, a control signal generating circuit 52 generates various control signals. The A port side and B port side of the dual port memory 50 each is provided with write data latches 53a, 53b, read data latches 54a, 54b, switches 55a-57b, select switches 58a, 58b, and tri-state buffers 59a and 59b, respectively, to perform arbitration all the time of access contention, in accordance with the control signal from control signal generating circuit 52.
    • 双端口存储器50包括与存储单元阵列100相关联的两个解码器9a,9b和两个读出放大器14a,14b。双端口存储器50可由A系统侧的CPU 6和 B系统侧同时。 CPU6和7相对于相同存储单元的访问之间的争用由访问争用检测电路51检测。响应于争用检测,控制信号产生电路52产生各种控制信号。 双端口存储器50的A端口侧和B端口侧各自设置有写数据锁存器53a,53b,读数据锁存器54a,54b,开关55a-57b,选择开关58a,58b和三态缓冲器59a和 59b分别根据来自控制信号发生电路52的控制信号执行访问争用的所有时间。