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1. 发明授权

US5107416A Arrangement for simultaneously dealing with transfer requests produced by central, arithmetic and input-output processors of a super computer 失效
标题翻译：同时处理超级计算机的中央，算术和输入输出处理器生成的传输要求的安排
公开(公告)号：US5107416A
公开(公告)日：1992-04-21
申请号：US290623
申请日：1988-12-27
申请人： Akira Jippo , Masafumi Okamoto , Tadashi Okano
发明人： Akira Jippo , Masafumi Okamoto , Tadashi Okano
IPC分类号： G06F13/12 , G06F13/28
CPC分类号： G06F13/122 , G06F13/28
摘要： For transfer of memory contents between an extended buffer memory and one of a first and a second main memory and of a peripheral storage device connected to an input-output processor, a transfer controlling arrangement can simultaneously receive transfer requests produced by a central processor, an arithmetic processor, and the input-output processor and can control the transfer requests. The transfer controlling arrangement comprises an extended buffer memory transfer controller connected to the central and the input-output processors through a first transfer controller, to the arithmetic processor through a second transfer controller, and to the extended buffer memory.
摘要翻译：为了在扩展缓冲存储器与第一和第二主存储器之一和连接到输入 - 输出处理器的外围存储设备之间传送存储器内容，转移控制装置可以同时接收由中央处理器产生的传送请求，算术处理器和输入输出处理器，并可以控制传输请求。转移控制装置包括通过第一传送控制器连接到中央和输入输出处理器的扩展缓冲存储器传送控制器，通过第二传送控制器和扩展缓冲存储器连接到算术处理器。

2. 发明授权

US06357033B1 Communication processing control apparatus and information processing system having the same 失效
标题翻译：通信处理控制装置及信息处理系统
公开(公告)号：US06357033B1
公开(公告)日：2002-03-12
申请号：US09262337
申请日：1999-03-04
申请人： Akira Jippo
发明人： Akira Jippo
IPC分类号： H03M1300
CPC分类号： H04L1/0061 , G06F11/1608 , H03M13/09 , H04L1/0045
摘要： A communication processing control apparatus for controlling data transmission between an arithmetic processing control apparatus and a network includes first and second communication processing sections, and a data control section. The first and second communication processing sections are made duplex and inserted into a duplex data transmission route to perform the same processing. The data control section adds CRC data to input data, and outputs the data to the first and second communication processing sections, and simultaneously checks the CRC data contained in output data from the first and second communication processing sections to detect a fault in the first and second communication processing sections.
摘要翻译：用于控制算术处理控制装置和网络之间的数据传输的通信处理控制装置包括第一和第二通信处理部分和数据控制部分。将第一和第二通信处理部分做成双工并插入到双工数据传输路由中以执行相同的处理。数据控制部分将CRC数据添加到输入数据，并将数据输出到第一和第二通信处理部分，同时检查来自第一和第二通信处理部分的输出数据中包含的CRC数据，以检测第一和第二通信处理部分的故障，第二通信处理部。

3. 发明授权

US5280606A Fault recovery processing for supercomputer 失效
标题翻译：超级计算机故障恢复处理
公开(公告)号：US5280606A
公开(公告)日：1994-01-18
申请号：US665955
申请日：1991-03-08
申请人： Akira Jippo , Akihiko Nakamura
发明人： Akira Jippo , Akihiko Nakamura
IPC分类号： G06F11/20 , G06F11/00 , G06F11/14 , G06F11/22 , G06F15/16 , G06F15/177 , G06F17/16
CPC分类号： G06F11/1417 , G06F11/0763 , G06F11/22
摘要： In a high speed computer having a memory and a plurality of arithmetic processors divided into groups, the arithmetic processors of each group being connected to the memory in a hierarchical order in a master-subordinate relationship, the memory and the arithmetic processors generates an alarm signal indicating a failed part of the memory and each of the arithmetic processors. During a fault recovery process, a test program is performed on the computer to determine if it is properly functioning. If a favorable result is indicated, the computer is restarted in an original system configuration. Otherwise, part of the arithmetic processors is isolated from the computer depending on the alarm signal to degrade the computer into a first degraded system configuration. The test program is performed again on the first degraded system configuration. If the second test produces a favorable result, the computer is restarted in the first degraded system configuration. Otherwise, one or more of the arithmetic processors are isolated from the computer depending on the alarm signal so that the computer is degraded into a second degraded system configuration.
摘要翻译：在具有存储器和分组的多个算术处理器的高速计算机中，每组的算术处理器以主从关系以分级顺序连接到存储器，存储器和算术处理器产生报警信号指示存储器和每个算术处理器的失败部分。在故障恢复过程中，在计算机上执行测试程序以确定其是否正常工作。如果指示有利的结果，则计算机将以原始系统配置重新启动。否则，根据报警信号，部分算术处理器与计算机隔离，从而将计算机降级为第一个降级的系统配置。在第一个降级的系统配置上再次执行测试程序。如果第二次测试产生有利的结果，则计算机在第一个降级的系统配置中重新启动。否则，根据报警信号，一个或多个算术处理器与计算机隔离，使得计算机被降级为第二降级系统配置。

4. 发明授权

US5860026A Information processing system for controlling operations of input/output devices of another clusters according to control instructions issued from a cluster 失效
标题翻译：用于根据从集群发出的控制指令来控制另一个集群的输入/输出设备的操作的信息处理系统
公开(公告)号：US5860026A
公开(公告)日：1999-01-12
申请号：US646547
申请日：1996-05-08
申请人： Michio Kitta , Akira Jippo
发明人： Michio Kitta , Akira Jippo
IPC分类号： G06F15/17 , H04L29/06 , G06F13/10
CPC分类号： H04L29/06 , H04L67/42
摘要： In an information processing system including a first cluster which issues a control instruction for controlling an input/output device of another cluster and a second cluster which executes processing by the input/output device according to the control instruction, which are connected through a network interconnecting clusters, a processor mounted on the first cluster comprises a cluster discrimination unit for discriminating a cluster which executes the control instruction and an instruction transfer unit for transferring the control instruction to the corresponding second cluster depending on the judgment of the cluster discrimination unit, while a data transfer processing device mounted on the second cluster comprises a transfer buffer for temporarily storing the data to be transferred to another cluster, a transfer buffer control unit for controlling reading and writing of the data from and into the transfer data storage unit, and a transfer control unit for controlling the transfer buffer control unit according to the control instruction from the first cluster.
摘要翻译：在包括第一集群的信息处理系统中，所述第一集群发布用于控制另一集群的输入/输出装置的控制指令，以及根据所述控制指令执行由所述输入/输出装置执行处理的第二集群，所述控制指令通过网络互连集群，安装在第一集群上的处理器包括用于鉴别执行控制指令的集群的集群鉴别单元和用于根据集群鉴别单元的判断将控制指令传送到对应的第二集群的指令传送单元，而安装在第二集群上的数据传送处理装置包括用于临时存储要传送到另一个集群的数据的传送缓冲器，用于控制从传送数据存储单元读取和写入数据的传送缓冲器控制单元，以及传送用于控制转运的控制单元 er缓冲器控制单元根据来自第一集群的控制指令。

5. 发明授权

US5301351A Data transfer control system between high speed main memory and input/output processor with a data mover 失效
标题翻译：高速主存储器与数据移动器的输入/输出处理器之间的数据传输控制系统
公开(公告)号：US5301351A
公开(公告)日：1994-04-05
申请号：US3685
申请日：1993-01-13
申请人： Akira Jippo
发明人： Akira Jippo
IPC分类号： G06F15/16 , G06F5/06 , G06F13/38 , G06F17/16 , G06F13/00
CPC分类号： G06F5/06
摘要： In a data processing method of this invention, data having an amount of a designated total data transfer length is transferred from a data buffer in a data mover to a designated start address of a control memory at a data transfer rate of a control data transfer control unit. Data having an amount of a designated block data transfer length is transferred from the buffer in the data mover to a designated start address of a high-speed arithmetic memory at a data transfer rate of a high-speed data transfer control unit.
摘要翻译：在本发明的数据处理方法中，具有指定的总数据传输长度的数据的数据以数据移动器中的数据缓冲器的形式被传送到控制存储器的指定的起始地址，控制数据传送控制的数据传送速率单元。具有指定块数据传送长度的数据的数据以高速数据传送控制单元的数据传送速率从数据移动器中的缓冲器传送到高速算术存储器的指定起始地址。

6. 发明授权

US5432915A Interprocessor communication system in an information processing system enabling communication between execution processor units during communication between other processor units 失效
标题翻译：信息处理系统中的处理器间通信系统，能够在其他处理器单元之间通信期间执行处理器单元之间的通信
公开(公告)号：US5432915A
公开(公告)日：1995-07-11
申请号：US730390
申请日：1991-07-15
申请人： Akira Jippo
发明人： Akira Jippo
IPC分类号： G06F15/16 , G06F9/46 , G06F9/52 , G06F13/362 , G06F15/17 , G06F15/177 , G06F13/00 , G06F13/36
CPC分类号： G06F9/52 , G06F13/362 , G06F15/17
摘要： An interprocessor communication system is used in an information processing system having a plurality of processor units. Those processor units are classified into a first group comprising control processor and IO processor units and into a second group comprising a plurality of execution processor units. In order to enable to start communication between two of the execution processors when one unit in the first group is performing communication with another one of the plurality of processor units, the interprocessor communication system comprises first through third locking circuits for issuing a first through third permission and then locking further issue of the first through third permissions, respectively. Two units in the first group communicate with each other after acquiring the first permission. Two units in the second group communicate with each other after acquiring the second permission. One unit in the first group communicates with one unit in second group after acquiring the third permission. Even when one unit in the first group is communicating with one unit in the second processor group, two other units in the second processor group can acquire the second permission to thereby communicate with each other.
摘要翻译：在具有多个处理器单元的信息处理系统中使用处理器间通信系统。这些处理器单元被分类为包括控制处理器和IO处理器单元的第一组，并且分为包括多个执行处理器单元的第二组。为了能够在第一组中的一个单元正在与多个处理器单元中的另一个执行通信时使得能够开始两个执行处理器之间的通信，处理器间通信系统包括用于发出第一至第三许可的第一至第三锁定电路然后分别锁定第一至第三权限的进一步发布。第一组中的两个单位在获得第一个许可之后相互通信。第二组中的两个单位在获得第二个许可之后相互通信。第一组中的一个单元在获得第三个许可之后与第二组中的一个单元进行通信。即使第一组中的一个单元正在与第二处理器组中的一个单元通信，则第二处理器组中的另外两个单元可以获取第二许可，从而彼此通信。

7. 发明授权

US5404477A Extended memory address conversion and data transfer control system 失效
标题翻译：扩展内存地址转换和数据传输控制系统
公开(公告)号：US5404477A
公开(公告)日：1995-04-04
申请号：US131876
申请日：1993-10-05
申请人： Akira Jippo
发明人： Akira Jippo
IPC分类号： G06F12/10 , G06F3/06 , G06F3/08 , G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F3/0601 , G06F12/0615 , G06F2003/0694
摘要： An extended memory address control system includes a disk address designation unit for managing the extended memory as a virtual disk, a disk address conversion unit for converting a virtual disk address designated by the disk address designation unit to a first physical address of the extended memory, a memory address designation unit for managing the extended memory as a continuous memory space, a memory address conversion unit for converting a memory address designated by the memory address designation unit to a second physical address of the extended memory, a type discrimination unit for discriminating whether the extended memory is managed as a virtual disk or a continuous memory space, and an access control unit for accessing the extended memory using one of the first and second physical addresses indicated by the type discrimination unit.
摘要翻译：扩展存储器地址控制系统包括用于管理作为虚拟盘的扩展存储器的盘地址指定单元，用于将由盘地址指定单元指定的虚拟盘地址转换为扩展存储器的第一物理地址的盘地址转换单元，用于将扩展存储器管理为连续存储器空间的存储器地址指定单元，用于将由存储器地址指定单元指定的存储器地址转换为扩展存储器的第二物理地址的存储器地址转换单元，用于鉴别是否扩展存储器被管理为虚拟盘或连续存储器空间，以及访问控制单元，用于使用类型识别单元指示的第一和第二物理地址之一访问扩展存储器。

8. 发明授权

US4872166A Information processing system capable of reducing invalid memory operations by detecting an error in a main memory 失效
标题翻译：信息处理系统能够通过检测主存储器中的错误来减少无效存储器操作
公开(公告)号：US4872166A
公开(公告)日：1989-10-03
申请号：US094582
申请日：1987-09-09
申请人： Akira Jippo
发明人： Akira Jippo
IPC分类号： G06F12/16 , G06F11/22 , G11C29/00 , G11C29/28 , G11C29/38
CPC分类号： G11C29/76 , G11C29/28 , G11C29/38 , G06F11/22
摘要： In an information processing system for use in detecting an error in a main memory (11) comprising a plurality of memory units (111 to 118) and a common control section (19), an error detection signal and an error address are sent from a request source processor (15) to a diagnostic address generator (31) when an error is detected on an access operation of the request source processor. On diagnostic access operations, the diagnostic address generator successively produces a plurality of diagnostic addresses including the error address to receive diagnostic replies, each of which comprises a reply code. When an error of the main memory is indicated by the reply code, an error detection controller (32) discriminates the diagnostic address on occurrence of the error in the diagnostic operations to disconnect the memory unit or units from the main memory by the use of a memory restructuring circuit (36). All of the memory units are disconnected when a malfunction of the common control section is discriminated by the error detection controller.
摘要翻译：在用于检测包括多个存储单元（111至118）和公共控制部分（19）的主存储器（11）中的错误的信息处理系统中，错误检测信号和错误地址从当在请求源处理器的访问操作上检测到错误时，将请求源处理器（15）发送到诊断地址生成器（31）。在诊断访问操作中，诊断地址产生器连续地产生多个诊断地址，包括错误地址以接收诊断回复，每个诊断地址包括回复代码。当主存储器的错误由回复代码指示时，错误检测控制器（32）在诊断操作中鉴别错误发生时的诊断地址，以通过使用主存储器来断开存储器单元与主存储器的连接存储器重构电路（36）。当由错误检测控制器识别公共控制部分的故障时，所有存储器单元断开。

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