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    • 4. 发明申请
    • Method of preparing fried rice
    • 炒饭的方法
    • US20050266133A1
    • 2005-12-01
    • US11135436
    • 2005-05-24
    • Teruo KobayashiTatuya YamamotoFumihiko SanoNaoki Matsubara
    • Teruo KobayashiTatuya YamamotoFumihiko SanoNaoki Matsubara
    • A23L7/10A23C3/00A23L7/196
    • A23L7/1965
    • A method of preparing industrially and inexpensively fried rice having nice-smelling, well-harmonized taste, soft on the inner side of the grains of the cooked rice and lightly separated at the surfaces thereof, and also suited to be freeze-preserved is disclosed. The method of preparing fried rice, including a rice washing step, a rice immersion step, a rice cooking step and a rice frying step. In this method, two frying steps 11, 15 are carried out in at least two stages out of a stage between a rice washing step 10 and rice immersion step 13, a stage between the immersion step 13 and cooking step 14, an intermediate stage of the cooking stage 14, and a latter stage of the cooking step 14, for example, in a stage between the washing step 10 and immersion step 13, and the latter stage of the cooking step 14.
    • 公开了一种制备工业上和廉价的炒饭的方法,其具有良好的气味,良好协调的味道,在米饭的谷粒的内侧是柔软的,并且在其表面上轻微分离,并且也适合于冷冻保存。 制备炒饭的方法,包括米饭洗涤步骤,米浸渍步骤,米饭烹饪步骤和炒饭步骤。 在这种方法中,两个油炸步骤11,15在大米洗涤步骤10和米浸渍步骤13之间的阶段中至少两个阶段进行,浸渍步骤13和烹饪步骤14之间的阶段,中间阶段 烹饪台14和烹调步骤14的后段,例如在洗涤步骤10和浸渍步骤13之间的阶段以及烹调步骤14的后一阶段。
    • 7. 发明授权
    • Pulser plate mounting structure
    • 喷浆板安装结构
    • US08770062B2
    • 2014-07-08
    • US12524515
    • 2008-01-29
    • Teruo KobayashiTakeru Hamakawa
    • Teruo KobayashiTakeru Hamakawa
    • F16C3/04
    • F16C3/12F02D41/009F16D1/076F16D2300/12
    • A pulser plate mounting structure is provided in which a key groove (14) is formed in a mounting face (10) of a rotating wall portion (9) formed from a crank arm (3) and a counterweight (4), a key portion (16) for engaging with the key groove (14) is formed on a pulser plate (P) that is superimposed on the mounting face (10), and this pulser plate (P) is secured to the rotating wall portion (9) by means of a securing member (18), wherein the key portion (16) is formed from an arched band-shaped portion (16a) projecting in an arched shape from the pulser plate (P) on one end face side thereof and engaging with the key groove (14), and a pair of connecting portions (16b) for providing integral connection between the pulser plate (P) and opposite ends of the arched band-shaped portion (16a). This provides a high precision of positioning of the pulser plate relative to the crankshaft and a good productivity for the pulser plate.
    • 提供了一种脉冲发生器安装结构,其中在由曲柄臂(3)和配重(4)形成的旋转壁部分(9)的安装面(10)上形成有键槽(14),键部分 在与叠置在安装面(10)上的脉冲发生器(P)上形成有用于与键槽(14)卡合的接头(16),该脉冲发生器板(P)通过 固定构件(18)的装置,其中,所述键部(16)由在其一个端面侧上从所述脉冲发生器板(P)以弓形形状突出的弓形带状部分(16a)形成, 以及用于提供脉冲发生器板(P)与拱形带状部分(16a)的相对端之间的整体连接的一对连接部分(16b)。 这提供了脉冲发生器相对于曲轴的定位的高精度,并且对于脉冲发生器板具有良好的生产率。
    • 10. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US4651190A
    • 1987-03-17
    • US788254
    • 1985-10-17
    • Hiroaki SuzukiTeruo Kobayashi
    • Hiroaki SuzukiTeruo Kobayashi
    • H01L21/822H01L21/82H01L21/8238H01L27/02H01L27/04H01L27/092H01L27/118H01L27/10
    • H01L27/11807H01L27/0207
    • A semiconductor integrated circuit includes p- and n-type semiconductor areas alternately arranged in a row direction, p-channel MOS transistor blocks arranged in each of the p-type semiconductor areas and each including two p-channel MOS transistors, n-channel MOS transistor blocks arranged in each of the n-type semiconductor areas and each including two n-channel MOS transistors, and p- and n-type diffusion areas formed, respectively, in each of the p-type semiconductor areas and in each of the n-type semiconductor areas. The MOS transistor blocks are arranged on two columns in each of the p- and n-type semiconductor areas, and each of the diffusion areas is formed in a position defined by the gate electrodes of four MOS transistors of the same channel type in the two MOS transistor blocks adjacent to each other in a row direction.
    • 半导体集成电路包括在行方向上交替布置的p型和n型半导体区域,配置在每个p型半导体区域中的p沟道MOS晶体管块,并且每个包括两个p沟道MOS晶体管,n沟道MOS 配置在每个n型半导体区域中并且每个包括两个n沟道MOS晶体管的晶体管块,以及分别形成在每个p型半导体区域中的每一个中的n型扩散区域和n个 型半导体领域。 MOS晶体管块被布置在p型和n型半导体区域中的每一个上的两列上,并且每个扩散区域形成在由两个相同沟道类型的四个MOS晶体管的栅电极限定的位置 MOS晶体管块在行方向上彼此相邻。