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1. 发明授权

US5508963A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5508963A
公开(公告)日：1996-04-16
申请号：US209120
申请日：1994-03-11
申请人： Akihiro Sawada , Hiroyuki Yamauchi , Hironori Akamatsu , Shunichi Iwanari , Masashi Agata , Hirohito Kikukawa , Hisakazu Kotani
发明人： Akihiro Sawada , Hiroyuki Yamauchi , Hironori Akamatsu , Shunichi Iwanari , Masashi Agata , Hirohito Kikukawa , Hisakazu Kotani
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/80 , G11C29/808 , G11C29/83 , G11C29/84 , G11C29/846
摘要： N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.
摘要翻译： N段冗余地址比较电路分别由阻抗转换电路组成，从而使用冗余的信息作为阻抗值传输。因此，即使当存储器的容量变大时N变大，具有大电容的信号线和冗余判断电路的节点也不被充电或放电。可以实现高速操作，而不受信号线的电容或冗余判断电路的节点的电容的影响。

2. 发明授权

US5719531A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5719531A
公开(公告)日：1998-02-17
申请号：US739841
申请日：1996-10-30
申请人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , H03F3/45
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

3. 发明授权

US5642323A Semiconductor integrated circuit with a data transmission circuit 失效
标题翻译：具有数据传输电路的半导体集成电路
公开(公告)号：US5642323A
公开(公告)日：1997-06-24
申请号：US573076
申请日：1995-12-15
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
摘要翻译：在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。在锁存电路锁存之后，停止放大电路的工作。驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

4. 发明授权

US5818782A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5818782A
公开(公告)日：1998-10-06
申请号：US814507
申请日：1997-03-10
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C13/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

5. 发明授权

US5680366A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
标题翻译：数据传输电路，数据线驱动电路，放大电路，半导体集成电路和半导体存储器
公开(公告)号：US5680366A
公开(公告)日：1997-10-21
申请号：US573133
申请日：1995-12-15
申请人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , H03K3/26
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
摘要翻译：在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。在锁存电路锁存之后，停止放大电路的工作。驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

6. 发明授权

US5515334A Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
公开(公告)号：US5515334A
公开(公告)日：1996-05-07
申请号：US260922
申请日：1994-06-15
申请人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
发明人： Hisakazu Kotani , Hironori Akamatsu , Ichiro Nakao , Toshio Yamada , Akihiro Sawada , Hirohito Kikukawa , Masashi Agata , Shunichi Iwanari
IPC分类号： G11C5/02 , G11C7/10 , G11C11/4096 , G11C7/00
CPC分类号： G11C7/1057 , G11C11/4096 , G11C5/025 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C7/1069
摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

7. 发明授权

US5426601A Semiconductor memory device having a prolonged data holding time 失效
标题翻译：半导体存储器件具有延长的数据保持时间
公开(公告)号：US5426601A
公开(公告)日：1995-06-20
申请号：US184933
申请日：1994-01-24
申请人： Masashi Agata , Hironori Akamatsu , Hirohito Kikukawa , Akihiro Sawada , Shunichi Iwanari
发明人： Masashi Agata , Hironori Akamatsu , Hirohito Kikukawa , Akihiro Sawada , Shunichi Iwanari
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C5/143
摘要： An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.
摘要翻译：外部电源电压VCC作为第一内部电源电压VPERI施加到外围电路。如果VCC在VCC推荐工作条件下规定的电压范围内VCC不大于下限电压V0L，则电源电压控制电路输出高逻辑电平的电压控制信号VSIG，否则输出低逻辑电平的VSIG。电源电路将第二内部电源电压VW和第三内部电源电压VWORD施加到存储单元部分。如果VSIG为高电平，则VW等于VPERI，而另一方面，VW是VPERI升压的电压。 VWORD是由于将VW进一步升高而产生的电压。行解码器将VW发送到一行读出放大器的使能信号线上，并将VWORD发送到存储单元阵列的字线上，以使VW成为存储单元的高逻辑电平数据写入电压。这样就可以在不牺牲存储单元耐压的情况下充分延长数据保持时间。

8. 发明授权

US5546346A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5546346A
公开(公告)日：1996-08-13
申请号：US354124
申请日：1994-12-06
申请人： Masashi Agata , Kazuhiro Matsuyama , Hironori Akamatsu , Hirohito Kikukawa , Akihiro Sawada , Shunichi Iwanari
发明人： Masashi Agata , Kazuhiro Matsuyama , Hironori Akamatsu , Hirohito Kikukawa , Akihiro Sawada , Shunichi Iwanari
IPC分类号： G11C11/409 , G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1072
摘要： In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.
摘要翻译：在需要与时钟信号同步执行高速连续操作的同步DRAM中，DBI线对连接在DQ线对和RDB线对之间，其流水线操作的单周期时间为分为四个阶段。该S-DRAM具有以下：第一预充电电路，用于仅在第一和第四周期中将DQ线对预充电或电压均衡至电源电压电平; 第二预充电电路，用于仅在第一和第二周期中将DBI线对对电压均衡至接地电压电平; 第三预充电电路，用于仅在第一和第二周期中将RDB线对对电压均衡至电源电压电平; 第一和第二差分放大器，用于在第三周期中将DQ线上的数据发送到DBI线上，并且用于在第四周期中将数据保存在DBI线上; 以及第三差分放大器，其在第三周期中将DBI线上的数据发送到RDB线上，并且在第四周期中将数据保存在RDB线上。

9. 发明授权

US5841727A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5841727A
公开(公告)日：1998-11-24
申请号：US867855
申请日：1997-06-03
申请人： Shunichi Iwanari , Hirohito Kikukawa
发明人： Shunichi Iwanari , Hirohito Kikukawa
IPC分类号： G11C11/408 , G11C8/12 , G11C11/401 , G11C11/406 , G11C8/00
CPC分类号： G11C8/12 , G11C11/406
摘要： To restrain an increase in power consumption and a reduction in access speed, the following structure is adopted: An address is input to a row address input circuit and in correspondence with a row address output from the row address input circuit, a predecode signal is output from a row predecode circuit. An address is input to a block-select-signal generating circuit from which first and second block select signals are output for selecting either one of the first and second memory cell array blocks. First and second predecode-signal hold circuits provided in correspondence with the first and second memory cell array blocks hold predecode signals. First and second predecode signals held by the first and second predecode signal hold circuits are supplied to first and second row decode circuits, respectively, and the first and second predecode-signal hold circuits corresponding to the first and second block select signals update the contents being held.
摘要翻译：为了抑制功耗的增加和存取速度的降低，采用以下结构：将地址输入到行地址输入电路，并且与从行地址输入电路输出的行地址对应地输出预解码信号来自一行预先解码电路。地址被输入到块选择信号发生电路，从其输出第一和第二块选择信号以选择第一和第二存储单元阵列块中的任一个。与第一和第二存储单元阵列块对应地设置的第一和第二预解码信号保持电路保持预解码信号。由第一和第二预解码信号保持电路保持的第一和第二预解码信号分别被提供给第一和第二行解码电路，并且对应于第一和第二块选择信号的第一和第二预解码信号保持电路更新内容为保持。

10. 发明申请

US20080313391A1 SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
标题翻译：半导体存储器件和半导体器件
公开(公告)号：US20080313391A1
公开(公告)日：2008-12-18
申请号：US12136340
申请日：2008-06-10
申请人： Shunichi Iwanari , Hisakazu Kotani , Masanori Matsuura
发明人： Shunichi Iwanari , Hisakazu Kotani , Masanori Matsuura
IPC分类号： G06F12/02
CPC分类号： G11C16/26 , G11C7/1039 , G11C7/1051 , G11C7/1063
摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.
摘要翻译：一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

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