专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070006025A1 Sending device, receiving device, communication control device, communication system, and communication control method 审中-公开
标题翻译：发送装置，接收装置，通信控制装置，通信系统和通信控制方法
公开(公告)号：US20070006025A1
公开(公告)日：2007-01-04
申请号：US11477440
申请日：2006-06-30
申请人： Akihiro Onozuka , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
发明人： Akihiro Onozuka , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
IPC分类号： G06F11/00
CPC分类号： H04L1/0046
摘要： The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.
摘要翻译：该系统在发送装置中具有生成包括数据的发送数据的发生器，从数据生成的数据错误检测码和表示可靠度的安全标志，以及发送数据; 在接收装置中具有从接收到的帧中提取发送数据，安全标志和数据错误检测码的多个组件，并且检测数据错误，比较多个接收帧的匹配的比较器，以及从帧错误检测结果，安全标志，数据错误检测结果和匹配比较结果中选择一个接收帧的选择器; 并通过与利用安全标志设定的可靠度相对应的检测来确定发送数据的有效性。

2. 发明申请

US20110022936A1 SENDING DEVICE, RECEIVING DEVICE, COMMUNICATION CONTROL DEVICE, COMMUNICATION SYSTEM, AND COMMUNICATION CONTROL METHOD 失效
标题翻译：发送装置，接收装置，通信控制装置，通信系统和通信控制方法
公开(公告)号：US20110022936A1
公开(公告)日：2011-01-27
申请号：US12900988
申请日：2010-10-08
申请人： Akihiro ONOZUKA , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
发明人： Akihiro ONOZUKA , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L1/0046
摘要： A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.
摘要翻译：一种接收装置，包括：接收器，接收两个帧，每个帧分别包括与数据错误检测码相关的基本相同的数据，帧错误检测码和表示安全功能的安全标志信息; 连接到接收机的第一检测器，分别通过使用帧错误检测码来进行帧的错误检测; 连接到所述接收器的第二检测器，用于分别通过使用所述数据检错码执行所述数据的错误检测; 以及连接到第一和第二检测器的直接存储器访问控制器（DMAC），用于在帧中没有检测到错误的两帧中的安全功能的条件下输出包括在两个帧中的数据之一，并且数据错误检测。

3. 发明授权

US08209594B2 Sending device, receiving device, communication control device, communication system, and communication control method 失效
标题翻译：发送装置，接收装置，通信控制装置，通信系统和通信控制方法
公开(公告)号：US08209594B2
公开(公告)日：2012-06-26
申请号：US12900988
申请日：2010-10-08
申请人： Akihiro Onozuka , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
发明人： Akihiro Onozuka , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H04L1/0046
摘要： A receiving device including: a receiver receiving two frames, each including substantially same data attached thereto with a data error detection code, a frame error detection code, and safety flag information indicating a safety function or not, respectively; a first detector connected to the receiver for performing error detection of the frames by use of the frame error detection code, respectively; a second detector connected to the receiver for performing error detection of the data by use of the data error detection code, respectively; and a Direct Memory Access Controller (DMAC) connected to the first and second detectors for outputting one among the data included in the two frames under a condition of the safety function in the two frames when no error is detected in the frame and data error detections.
摘要翻译：一种接收装置，包括：接收器，接收两个帧，每个帧分别包括与数据错误检测码相关的基本相同的数据，帧错误检测码和表示安全功能的安全标志信息; 连接到接收机的第一检测器，分别通过使用帧错误检测码来进行帧的错误检测; 连接到所述接收器的第二检测器，用于分别通过使用所述数据检错码执行所述数据的错误检测; 以及连接到第一和第二检测器的直接存储器访问控制器（DMAC），用于在帧中没有检测到错误的两帧中的安全功能的条件下输出包括在两个帧中的数据之一，并且数据错误检测。

4. 发明授权

US07555627B2 Input-output control apparatus, input-output control method, process control apparatus and process control method 有权
标题翻译：输入输出控制装置，输入输出控制方法，过程控制装置和过程控制方法
公开(公告)号：US07555627B2
公开(公告)日：2009-06-30
申请号：US11477468
申请日：2006-06-30
申请人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
发明人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/122 , Y02P90/14
摘要： Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
摘要翻译：通过提供输入输出控制装置，通过提供输入输出控制装置来防止输入输出装置由于处理器使用的输入输出值，以便以具有较高安全性要求的模式进行算术运算第一存储区域，存储由处理器在具有相对较低安全性要求的模式下进行算术运算的输入输出值，并将其限制在第一存储区域中，并将复制从第一存储区域区域，复制到第二存储区域，或者根据关于安全性要求的模式从第二存储区域进行复制。

5. 发明申请

US20070239916A1 Input-output control apparatus, input-output control method, process control apparatus and process control method 有权
标题翻译：输入输出控制装置，输入输出控制方法，过程控制装置和过程控制方法
公开(公告)号：US20070239916A1
公开(公告)日：2007-10-11
申请号：US11477468
申请日：2006-06-30
申请人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
发明人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
IPC分类号： G06F12/14
CPC分类号： G06F13/122 , Y02P90/14
摘要： Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
摘要翻译：通过提供输入输出控制装置，通过提供输入输出控制装置来防止输入输出装置由于处理器使用的输入输出值，以便以具有较高安全性要求的模式进行算术运算第一存储区域，存储由处理器在具有相对较低安全性要求的模式下进行算术运算的输入输出值，并将其限制在第一存储区域中，并将复制从第一存储区域区域，复制到第二存储区域，或者根据关于安全性要求的模式从第二存储区域进行复制。

6. 发明申请

US20060282702A1 Task management apparatus for control apparatus, input/output control apparatus, information control apparatus, task management method, input/output controlling method, and information controlling method 有权
标题翻译：控制装置的任务管理装置，输入输出控制装置，信息控制装置，任务管理方法，输入输出控制方法以及信息控制方法
公开(公告)号：US20060282702A1
公开(公告)日：2006-12-14
申请号：US11447724
申请日：2006-06-07
申请人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masahiro Shiraishi , Masakazu Ishikawa , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
发明人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masahiro Shiraishi , Masakazu Ishikawa , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
IPC分类号： G05B9/02 , G06F11/00
CPC分类号： G06F9/3851 , G06F9/30189 , G06F9/3885 , G06F11/1641 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F2201/845
摘要： Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.
摘要翻译：当处理器对公共对象的数据进行兼容计算时，接收到处理的结果。响应于来自任一个处理器的启动信号，生成计算命令信号并将其馈送到处理器，使得处理器可以利用不同的操作定时进行计算。然后，将处理器进行的计算的结果相互比较。因此，可以通过使用处理器的上述结构来实现同时具有小尺寸，高性能和安全性的装置。

7. 发明授权

US08161362B2 Task management control apparatus and method, having redundant processing comparison 有权
标题翻译：任务管理控制装置和方法，具有冗余处理比较
公开(公告)号：US08161362B2
公开(公告)日：2012-04-17
申请号：US11447724
申请日：2006-06-07
申请人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masakazu Ishikawa , Masahiro Shiraishi , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
发明人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masakazu Ishikawa , Masahiro Shiraishi , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
IPC分类号： G06F11/00 , G06F7/02
CPC分类号： G06F9/3851 , G06F9/30189 , G06F9/3885 , G06F11/1641 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F2201/845
摘要： Processed results are received when processors make compatible computations on data of a common object. A computation command signal is generated and fed to the processors in response to a start signal from any one of the processors so that the processors can make computations with different operation timings. Then, the results of the computations made by the processors are compared with each other. Thus, apparatus capable of small size, high performance and safety at the same time can be achieved by the above construction using the processors.
摘要翻译：当处理器对公共对象的数据进行兼容计算时，接收到处理的结果。响应于来自任一个处理器的启动信号，生成计算命令信号并将其馈送到处理器，使得处理器可以用不同的操作定时进行计算。然后，将处理器进行的计算的结果相互比较。因此，可以通过使用处理器的上述结构来实现同时具有小尺寸，高性能和安全性的装置。

8. 发明申请

US20110214125A1 TASK MANAGEMENT CONTROL APPARATUS AND METHOD HAVING REDUNDANT PROCESSING COMPARISON 审中-公开
标题翻译：任务管理控制装置和具有冗余处理对比的方法
公开(公告)号：US20110214125A1
公开(公告)日：2011-09-01
申请号：US13105041
申请日：2011-05-11
申请人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masakazu Ishikawa , Masahiro Shiraishi , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
发明人： Akira Bando , Shin Kokura , Takashi Umehara , Masamitsu Kobayashi , Hisao Nagayama , Naoya Mashiko , Masakazu Ishikawa , Masahiro Shiraishi , Akihiro Onozuka , Hiromichi Endoh , Tsutomu Yamada , Satoru Funaki
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/30189 , G06F9/3885 , G06F11/1641 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F2201/845
摘要： An input/output control apparatus including: a unit that controls input/output of data relating to a computation of a plurality of processors in response to an access request from a second input/output unit and an access request from a first input/output unit which requires higher reliability than said second input/output unit, and orders at least one of a plurality of processors to perform a computation relating to the access request from said first input/output unit away from the computation relating to the access request from said second input/output unit in case of that said first input/output unit issued an access request, so that a same computation is made by said plurality of processors; a unit that compares the results of said computations relative to the access request from said first input/output unit provided from said plurality of processors; and a unit that allows the data associated with said computations of said processors to be output on the basis of said compared results.
摘要翻译：一种输入/输出控制装置，包括：响应于来自第二输入/输出单元的访问请求和来自第一输入/输出单元的访问请求来控制与多个处理器的计算有关的数据的输入/输出的单元其要求比所述第二输入/输出单元更高的可靠性，并且命令多个处理器中的至少一个处理器执行与来自所述第一输入/输出单元的访问请求相关的计算，远离与所述第二输入/输出单元的访问请求有关的计算在所述第一输入/输出单元发出访问请求的情况下，输入/输出单元，使得所述多个处理器进行相同的计算; 从所述多个处理器提供的所述第一输入/输出单元中比较所述计算结果与所述访问请求的单元; 以及允许基于所述比较结果输出与所述处理器的所述计算相关联的数据的单元。

9. 发明申请

US20070055480A1 System and method for self-diagnosis in a controller 审中-公开
标题翻译：控制器中自诊断的系统和方法
公开(公告)号：US20070055480A1
公开(公告)日：2007-03-08
申请号：US11514273
申请日：2006-09-01
申请人： Hiromichi Endoh , Tsutomu Yamada , Naoya Mashiko , Takashi Umehara
发明人： Hiromichi Endoh , Tsutomu Yamada , Naoya Mashiko , Takashi Umehara
IPC分类号： G21C17/00
CPC分类号： G06F11/27
摘要： A self-diagnosis system of a processor capable of realizing a sufficiently high processing ability for control tasks is provided without deteriorating reliability of safety controls even in complex diagnostic techniques. The self-diagnosis system is equipped with a diagnostic target area allocator for allocating a non-active area within a memory as a diagnosis-ready area, which is not used in a control task under execution by a main processor in an independent manner from the main processor; and a diagnostic executor for executing a diagnosis based upon a predetermined sequence in an independent manner from the main processor. In the self-diagnosis system, a diagnostic target area segmented from the diagnosis-ready area is selected, and a diagnosis of the selected diagnostic target area is carried out in each of diagnostic cycles by the diagnostic executor.
摘要翻译：提供了能够实现足够高的控制任务处理能力的处理器的自我诊断系统，而不会恶化安全控制的可靠性，即使在复杂的诊断技术中。自诊断系统配备有用于将存储器内的非有效区域分配为诊断就绪区域的诊断目标区域分配器，其不被主处理器执行的控制任务中以独立的方式从主处理器以及诊断执行器，用于基于来自主处理器的独立方式基于预定顺序执行诊断。在自诊断系统中，选择从诊断就绪区域分割的诊断对象区域，并且通过诊断执行器在每个诊断周期中进行所选择的诊断对象区域的诊断。

10. 发明授权

US07716405B2 Computer system 失效
标题翻译：电脑系统
公开(公告)号：US07716405B2
公开(公告)日：2010-05-11
申请号：US11599383
申请日：2006-11-15
申请人： Tsutomu Yamada , Hiromichi Endoh , Noritaka Matsumoto , Satoru Funaki , Tatsuya Maruyama , Atsushi Ito , Fumiyuki Tamura , Norihisa Yanagihara , Makiko Naemura
发明人： Tsutomu Yamada , Hiromichi Endoh , Noritaka Matsumoto , Satoru Funaki , Tatsuya Maruyama , Atsushi Ito , Fumiyuki Tamura , Norihisa Yanagihara , Makiko Naemura
IPC分类号： G06F13/36
CPC分类号： G06F13/37
摘要： A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.
摘要翻译：一种作为堆叠总线系统的计算机系统，其中多个计算机模块彼此堆叠并彼此连接并且能够自动匹配和分配诸如时钟和中断的总线资源。在包括一个系统模块和n个外围模块的计算机系统中，每个外围模块包括中断选择器，时钟选择器，仲裁信号选择器，资源判定单元和位置识别单元。所述位置识别单元与存在于所述系统模块中的位置配置单元配合，以在所述计算机系统中识别包括所述位置识别单元的模块的位置，并且自主地决定所述模块使用的总线资源。通过允许中断选择器，时钟选择器和仲裁信号选择器来选择和使用所决定的总线资源，每个外围模块可以匹配和配置计算机系统中的总线资源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式