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1. 发明申请

US20130221385A1 LIGHT EMITTING ELEMENT AND PRODUCTION METHOD FOR SAME, PRODUCTION METHOD FOR LIGHT-EMITTING DEVICE, ILLUMINATION DEVICE, BACKLIGHT, DISPLAY DEVICE, AND DIODE 有权
标题翻译：发光元件及其制造方法，发光装置的制造方法，照明装置，背光，显示装置和二极管
公开(公告)号：US20130221385A1
公开(公告)日：2013-08-29
申请号：US13820081
申请日：2011-06-22
申请人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
发明人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
IPC分类号： H01L33/64 , H01L33/58 , H01L33/08 , H01L33/42
CPC分类号： H01L33/64 , G02F1/133603 , H01L25/0753 , H01L31/035227 , H01L31/03529 , H01L31/052 , H01L31/054 , H01L31/0547 , H01L33/0079 , H01L33/08 , H01L33/14 , H01L33/18 , H01L33/20 , H01L33/24 , H01L33/26 , H01L33/32 , H01L33/42 , H01L33/58 , H01L2924/0002 , Y02E10/52 , H01L2924/00
摘要： A light-emitting element includes a first conductivity type semiconductor base, a plurality of first conductivity type protrusion-shaped semiconductors formed on the semiconductor base, and a second conductivity type semiconductor layer that covers the protrusion-shaped semiconductors.
摘要翻译：发光元件包括第一导电型半导体基底，形成在半导体基底上的多个第一导电型突起状半导体，以及覆盖突起状半导体的第二导电型半导体层。

2. 发明授权

US09190590B2 Light emitting element and production method for same, production method for light-emitting device, illumination device, backlight, display device, and diode 有权
标题翻译：发光元件及其制造方法，发光装置，照明装置，背光源，显示装置和二极管的制造方法
公开(公告)号：US09190590B2
公开(公告)日：2015-11-17
申请号：US13820081
申请日：2011-06-22
申请人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
发明人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
IPC分类号： H01L33/20 , H01L33/64 , H01L33/58 , H01L33/08 , H01L31/052 , H01L33/14 , H01L33/26 , H01L25/075 , H01L33/18 , H01L33/24 , H01L31/0352 , H01L31/054 , H01L33/42 , G02F1/1335 , H01L33/00 , H01L33/32
CPC分类号： H01L33/64 , G02F1/133603 , H01L25/0753 , H01L31/035227 , H01L31/03529 , H01L31/052 , H01L31/054 , H01L31/0547 , H01L33/0079 , H01L33/08 , H01L33/14 , H01L33/18 , H01L33/20 , H01L33/24 , H01L33/26 , H01L33/32 , H01L33/42 , H01L33/58 , H01L2924/0002 , Y02E10/52 , H01L2924/00
摘要： A light-emitting element includes a first conductivity type semiconductor base, a plurality of first conductivity type protrusion-shaped semiconductors formed on the semiconductor base, and a second conductivity type semiconductor layer that covers the protrusion-shaped semiconductors.
摘要翻译：发光元件包括第一导电型半导体基底，形成在半导体基底上的多个第一导电型突起状半导体，以及覆盖突起状半导体的第二导电型半导体层。

3. 发明授权

US09181630B2 Method for disposing fine objects, apparatus for arranging fine objects, illuminating apparatus and display apparatus 有权
标题翻译：微细物体的配置方法，微细物体的配置装置，照明装置和显示装置
公开(公告)号：US09181630B2
公开(公告)日：2015-11-10
申请号：US13809433
申请日：2011-06-14
申请人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
发明人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
IPC分类号： H01L21/00 , H01L21/20 , H01L21/36 , C25D13/00 , H01L21/479 , H01L25/075 , H01L23/00 , H01L33/24 , H01L27/15 , H01L33/18 , H01L33/32
CPC分类号： C25D13/00 , H01L21/479 , H01L24/75 , H01L24/80 , H01L24/95 , H01L24/97 , H01L25/0753 , H01L27/156 , H01L33/18 , H01L33/24 , H01L33/32 , H01L2224/08238 , H01L2224/75655 , H01L2224/75723 , H01L2224/7598 , H01L2224/80143 , H01L2224/95101 , H01L2224/95145 , H01L2224/97 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
摘要： This method for disposing fine objects, in a substrate preparing step, prepares a substrate having specified positions where fine objects (120) are to be disposed in an area where a first electrode (111) and a second electrode (112) face each other, and in a fluid introducing step, a fluid (121) is introduced on the substrate (110). The fluid (121) contains a plurality of the fine objects (120). The fine objects (120) are diode elements, each of which has, as an alignment structure, a front side layer (130) composed of a dielectric material, and a rear side layer (131) composed of a semiconductor. In the fine object disposing step, by applying an AC voltage to between the first electrode (111) and the second electrode (112), the fine objects (120) are disposed by dielectrophoresis with the front side layer (130) facing up at the predetermined positions in the area (A) where the first electrode (111) and the second electrode (112) face each other.
摘要翻译：用于配置细小物体的方法在基板准备步骤中，准备在第一电极（111）和第二电极（112）彼此面对的区域中具有细微物体（120）的特定位置的基板，并且在流体引入步骤中，将流体（121）引入到所述基板（110）上。流体（121）包含多个精细物体（120）。精细物体（120）是二极管元件，每个二极管元件具有作为对准结构的由电介质材料构成的前侧层（130）和由半导体构成的后侧层（131）。在微细物体设置步骤中，通过在第一电极（111）和第二电极（112）之间施加AC电压，通过介电电泳设置微细物体（120），其中前侧层（130）面向上在第一电极（111）和第二电极（112）彼此面对的区域（A）中的预定位置。

4. 发明申请

US20130168708A1 METHOD FOR DISPOSING FINE OBJECTS, APPARATUS FOR ARRANGING FINE OBJECTS, ILLUMINATING APPARATUS AND DISPLAY APPARATUS 有权
标题翻译：处理精细物体的方法，安装精细物体的装置，照明装置和显示装置
公开(公告)号：US20130168708A1
公开(公告)日：2013-07-04
申请号：US13809433
申请日：2011-06-14
申请人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
发明人： Akihide Shibata , Tetsu Negishi , Kenji Komiya , Yoshifumi Yaoi , Takeshi Shiomi , Hiroshi Iwata , Akira Takahashi
IPC分类号： C25D13/00 , H01L27/15 , H01L21/479
CPC分类号： C25D13/00 , H01L21/479 , H01L24/75 , H01L24/80 , H01L24/95 , H01L24/97 , H01L25/0753 , H01L27/156 , H01L33/18 , H01L33/24 , H01L33/32 , H01L2224/08238 , H01L2224/75655 , H01L2224/75723 , H01L2224/7598 , H01L2224/80143 , H01L2224/95101 , H01L2224/95145 , H01L2224/97 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
摘要： This method for disposing fine objects, in a substrate preparing step, prepares a substrate having specified positions where fine objects (120) are to be disposed in an area where a first electrode (111) and a second electrode (112) face each other, and in a fluid introducing step, a fluid (121) is introduced on the substrate (110). The fluid (121) contains a plurality of the fine objects (120). The fine objects (120) are diode elements, each of which has, as an alignment structure, a front side layer (130) composed of a dielectric material, and a rear side layer (131) composed of a semiconductor. In the fine object disposing step, by applying an AC voltage to between the first electrode (111) and the second electrode (112), the fine objects (120) are disposed by dielectrophoresis with the front side layer (130) facing up at the predetermined positions in the area (A) where the first electrode (111) and the second electrode (112) face each other.
摘要翻译：用于配置细小物体的方法在基板准备步骤中，准备在第一电极（111）和第二电极（112）彼此面对的区域中具有细微物体（120）的特定位置的基板，并且在流体引入步骤中，将流体（121）引入到所述基板（110）上。流体（121）包含多个精细物体（120）。精细物体（120）是二极管元件，每个二极管元件具有作为对准结构的由电介质材料构成的前侧层（130）和由半导体构成的后侧层（131）。在微细物体设置步骤中，通过在第一电极（111）和第二电极（112）之间施加AC电压，通过介电电泳设置微细物体（120），其中前侧层（130）面向上在第一电极（111）和第二电极（112）彼此面对的区域（A）中的预定位置。

5. 发明申请

US20110089850A1 LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：发光装置及其制造方法
公开(公告)号：US20110089850A1
公开(公告)日：2011-04-21
申请号：US12904788
申请日：2010-10-14
申请人： Akihide Shibata , Tetsu Negishi , Satoshi Morishita , Kenji Komiya , Hiroshi Iwata , Akira Takahashi , Yoshifumi Yaoi
发明人： Akihide Shibata , Tetsu Negishi , Satoshi Morishita , Kenji Komiya , Hiroshi Iwata , Akira Takahashi , Yoshifumi Yaoi
IPC分类号： H05B37/02 , H01L33/00 , H01L33/36
CPC分类号： H05B33/0806 , H05B33/0803 , H05B33/0821
摘要： In a light emitting device, a P-type first region (506) and a P-type third region (508) are placed on both sides of an N-type second region (507) of a rod-like light emitting element (505). Therefore, even if connection of the first, third regions (506, 508) of the rod-like light emitting element (505) relative to the first, third electrodes (1, 3) is reversed, a diode polarity relative to the first, third electrodes (501, 503) is not reversed, making it possible to effectuate normal light emission. Thus, a connection of the first, third regions (506, 508) relative to the first, third electrodes (501, 503) may be reversed during a manufacturing process, making it unnecessary to provide marks or configurations for discrimination of orientation of the rod-like light emitting element (505), so that the manufacturing process can be simplified and manufacturing cost can be cut down.
摘要翻译：在发光装置中，在杆状发光元件（505）的N型第二区域（507）的两侧配置P型第一区域（506）和P型第三区域（508））。因此，即使棒状发光元件（505）的第一，第三区域（506,508）相对于第一，第三电极（1,3）的连接相反，二极管极性相对于第一，第三电极（501,503）不反转，可以实现正常的发光。因此，在制造过程中第一，第三区域（506,508）相对于第一，第三电极（501,503）的连接可以反转，使得不需要提供用于区分杆的取向的标记或构造样的发光元件（505），从而能够简化制造工序，能够削减制造成本。

6. 发明授权

US09293984B2 Illumination apparatus and power supply circuit 有权
标题翻译：照明装置和电源电路
公开(公告)号：US09293984B2
公开(公告)日：2016-03-22
申请号：US13598363
申请日：2012-08-29
申请人： Kenji Komiya , Takeshi Shiomi , Yoshifumi Yaoi , Masaru Nomura , Kohichiroh Adachi , Yoshiji Ohta , Hiroshi Iwata
发明人： Kenji Komiya , Takeshi Shiomi , Yoshifumi Yaoi , Masaru Nomura , Kohichiroh Adachi , Yoshiji Ohta , Hiroshi Iwata
IPC分类号： H02H7/125 , H02M1/42 , H05B33/08 , H02M3/158
CPC分类号： H02M1/4225 , H02M3/1582 , H02M2001/4291 , H05B33/0815 , Y02B20/346 , Y02B70/126
摘要： In order to offer a power supply circuit that can minimize the drop in efficiency by reducing losses during voltage conversion, in an improved-power factor circuit, a control circuit performs a step-up operation in which a control signal for turning on a first switching element (Tr1) and switching a second switching element (Tr2) is output, and a step-down operation in which a control signal for turning off the second switching element (Tr2) and switching the first switching element (Tr1) is output.
摘要翻译：为了提供能够通过减少电压转换时的损耗来最小化效率下降的电源电路，在改进的功率因数电路中，控制电路执行升压操作，其中用于接通第一开关的控制信号输出元件（Tr1）并切换第二开关元件（Tr2），并且输出用于关闭第二开关元件（Tr2）的控制信号和切换第一开关元件（Tr1）的降压操作。

7. 发明申请

US20130049620A1 ILLUMINATION APPARATUS AND POWER SUPPLY CIRCUIT 有权
标题翻译：照明设备和电源电路
公开(公告)号：US20130049620A1
公开(公告)日：2013-02-28
申请号：US13598363
申请日：2012-08-29
申请人： Kenji KOMIYA , Takeshi Shiomi , Yoshifumi Yaoi , Masaru Nomura , Kohichiroh Adachi , Yoshiji Ohta , Hiroshi Iwata
发明人： Kenji KOMIYA , Takeshi Shiomi , Yoshifumi Yaoi , Masaru Nomura , Kohichiroh Adachi , Yoshiji Ohta , Hiroshi Iwata
IPC分类号： G05F3/08 , H02M7/04 , H05B37/00 , H02M7/217
CPC分类号： H02M1/4225 , H02M3/1582 , H02M2001/4291 , H05B33/0815 , Y02B20/346 , Y02B70/126
摘要： In order to offer a power supply circuit that can minimize the drop in efficiency by reducing losses during voltage conversion, in an improved-power factor circuit, a control circuit performs a step-up operation in which a control signal for turning on a first switching element (Tr1) and switching a second switching element (Tr2) is output, and a step-down operation in which a control signal for turning off the second switching element (Tr2) and switching the first switching element (Tr1) is output.
摘要翻译：为了提供能够通过减少电压转换时的损耗来最小化效率下降的电源电路，在改进的功率因数电路中，控制电路执行升压操作，其中用于接通第一开关的控制信号输出元件（Tr1）并切换第二开关元件（Tr2），并且输出用于关闭第二开关元件（Tr2）的控制信号和切换第一开关元件（Tr1）的降压操作。

8. 发明授权

US07170791B2 Programming verification method of nonvolatile memory cell, semiconductor memory device, and portable electronic apparatus having the semiconductor memory device 有权
标题翻译：具有半导体存储器件的非易失性存储单元，半导体存储器件和便携式电子设备的编程验证方法
公开(公告)号：US07170791B2
公开(公告)日：2007-01-30
申请号：US10848236
申请日：2004-05-19
申请人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C16/06
CPC分类号： H01L29/66825 , G11C11/22 , G11C16/0475 , G11C16/3454 , G11C16/3459 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/66833 , H01L29/7887
摘要： A programming verification method of verifying programming of a nonvolatile memory cell, the method comprising at least the steps of: selecting first, second, . . . and n-th references corresponding to first, second, . . . and n-th threshold voltages specifying lower limit values of states 1, 2, . . . and n, respectively; applying a programming voltage to the nonvolatile memory cell; sensing a threshold voltage level of the nonvolatile memory cell; comparing the sensed threshold voltage level with the first reference to output a first result; comparing the threshold voltage level with one of the second and third references selected according to the first result to output a second result; and comparing the first and second results with an expectation value and, in the case where the first and second results are equal to the expectation value, indicating that the programming has succeeded, wherein the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, a source and a drain as diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having the function of retaining charges.
摘要翻译：一种验证非易失性存储单元的编程的编程验证方法，所述方法至少包括以下步骤：选择第一，第二，。。和对应于第一，第二的第n个引用。。。和指定状态1,2的下限值的第n阈值电压。。。和n; 向非易失性存储单元施加编程电压; 感测所述非易失性存储单元的阈值电压电平; 将感测到的阈值电压电平与第一参考值进行比较以输出第一结果; 将阈值电压电平与根据第一结果选择的第二和第三参考中的一个进行比较以输出第二结果; 以及将所述第一和第二结果与期望值进行比较，并且在所述第一和第二结果等于期望值的情况下，指示所述编程已成功，其中所述非易失性存储单元包括形成在半导体层上的栅电极通过栅极绝缘膜，设置在栅极电极下方的沟道区域，作为扩散区域的源极和漏极，设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型，以及存储功能单元栅电极的两侧并具有保持电荷的功能。

9. 发明授权

US07102941B2 Semiconductor memory device and portable electronic apparatus 有权
标题翻译：半导体存储器件和便携式电子设备
公开(公告)号：US07102941B2
公开(公告)日：2006-09-05
申请号：US10847625
申请日：2004-05-18
申请人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Masaru Nawaki , Yasuaki Iwase , Yoshinao Morikawa
发明人： Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Masaru Nawaki , Yasuaki Iwase , Yoshinao Morikawa
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C16/0475 , G11C29/78
摘要： A semiconductor memory device including (A) a global line; (B) a memory array having (i) a local line, (ii) a decoder connected to the global line and the local line, and (iii) a memory block and a redundant block each constructed by a plurality of memory cells each having a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed below the gate electrode, a diffusion region disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and a memory functional unit formed on both sides of the gate electrode and having the function of retaining charges, the memory array having the function that when the decoder is usable, the global line is selectively connected to one of the local lines in accordance with address information and, when a defective block is included in the memory blocks and the decoder is unusable, the local line is separated from the global line and the defective block is replaced with the redundant block; and (C) a circuit for making the decoder of the defective block unusable and, only when the defective block is addressed, for making the decoder of the redundant block usable.
摘要翻译：一种半导体存储器件，包括（A）全局线; （B）具有（i）本地线的存储器阵列，（ii）连接到全局线和本地线的解码器，以及（iii）由多个存储器单元构成的存储器块和冗余块，每个存储器单元和通过栅极绝缘膜形成在半导体层上的栅极电极，设置在栅极电极下方的沟道区域，设置在沟道区域两侧并且具有与沟道区域相反的导电类型的扩散区域;以及存储器功能单元形成在栅电极的两侧并且具有保持电荷的功能，该存储器阵列具有当解码器可用时的功能，全局线根据地址信息有选择地连接到一条局部线路，当存储块中包含有缺陷块并且解码器不可用时，本地线与全局线分离，并且用冗余块替换缺陷块; 以及（C）用于使缺陷块的解码器不可用的电路，并且仅当寻址缺陷块时，才能使冗余块的解码器可用。

10. 发明申请

US20050002263A1 Writing control method and writing control system of semiconductor storage device, and portable electronic apparatus 失效
标题翻译：半导体存储装置的写入控制方法和写入控制系统以及便携式电子设备
公开(公告)号：US20050002263A1
公开(公告)日：2005-01-06
申请号：US10848082
申请日：2004-05-19
申请人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
发明人： Yasuaki Iwase , Yoshifumi Yaoi , Hiroshi Iwata , Akihide Shibata , Yoshinao Morikawa , Masaru Nawaki
IPC分类号： G11C16/02 , G11C16/24 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/24
摘要： A writing control system providing high-speed writing to a nonvolatile semiconductor storage device, includes (a) a plurality of memory elements each having: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion region provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member, provided on both sides of the gate electrode, having a function of holding electric charges, (b) a memory array including a page buffer circuit, and (c) CPU controlling writing to the memory array. The CPU loads a first plane of the page buffer circuit with a first byte of data and writes with the first byte of data stored in the first plane. Further, the CPU writes a second byte of data into the second plane and writes the second byte of data having been stored in the second plane while writing the first byte of data having been stored in the first plane into the memory array.
摘要翻译：一种向非易失性半导体存储装置提供高速写入的写入控制系统，包括：（a）多个存储元件，每个存储元件具有：设置在具有中间栅极绝缘膜的半导体层上的栅电极; 设置在栅电极下方的沟道区; 扩散区，设置在沟道区的两侧，具有与沟道区相反的极性; 以及设置在栅电极的两侧上的具有保持电荷功能的存储器功能部件，（b）包括页缓冲电路的存储器阵列，（c）CPU控制对存储器阵列的写入。 CPU用第一个数据字节加载页面缓冲电路的第一个平面，并用第一个平面中存储的数据的第一个字节进行写入。此外，CPU将第二字节的数据写入第二平面，并且将已经存储在第一平面中的数据的第一字节写入存储器阵列中，将已经存储在第二平面中的数据的第二字节写入。

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