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1. 发明授权

US07682988B2 Thermal treatment of nitrided oxide to improve negative bias thermal instability 有权
标题翻译：氮化氧化物的热处理以改善负偏压热不稳定性
公开(公告)号：US07682988B2
公开(公告)日：2010-03-23
申请号：US10930230
申请日：2004-08-31
申请人： Husam N. Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy A. Chancellor , Anand Krishnan , Malcolm J. Bevan
发明人： Husam N. Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy A. Chancellor , Anand Krishnan , Malcolm J. Bevan
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8234
CPC分类号： H01L21/02326 , H01L21/0214 , H01L21/02337 , H01L21/265 , H01L21/28202 , H01L21/3144 , H01L21/823857 , H01L29/518 , H01L29/7833
摘要： A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
摘要翻译：一种降低在温度和电压应力之后导致的MOSFET晶体管的阈值电压偏移的方法，以及根据该方法制造的集成电路器件。该方法包括以下步骤：在半导体衬底上形成氮化介电层，并将氮化介电层在低压下进行退火。

2. 发明授权

US07514308B2 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US07514308B2
公开(公告)日：2009-04-07
申请号：US11745930
申请日：2007-05-08
申请人： Ajith Varghese , Husam N. Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam N. Alshareef , Rajesh Khamankar
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

3. 发明授权

US06924239B2 Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using “spike” radical oxidation 有权
标题翻译：使用“尖峰”自由基氧化在非热氮化之前去除栅极氧化物上的烃污染的方法
公开(公告)号：US06924239B2
公开(公告)日：2005-08-02
申请号：US10684897
申请日：2003-10-14
申请人： Hiroaki Niimi , Husam N. Alshareef , Ajith Varghese
发明人： Hiroaki Niimi , Husam N. Alshareef , Ajith Varghese
IPC分类号： H01L21/20 , H01L21/28 , H01L21/302 , H01L21/306 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/36
CPC分类号： H01L21/28202 , H01L21/02046 , H01L21/28185 , H01L21/3144 , H01L21/31662
摘要： The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.
摘要翻译：本发明一般涉及一种在氮化步骤之前从基底去除烃类污染物的方法，其中提供基底的大致均匀的氮化。该方法包括将基板放置在处理室中并将氧源气体流入处理室。第一等离子体在处理室中形成第一预定量的时间，其中烃与一种或多种以自由基形式的氧源气体组合以形成产物气体。气体从处理室中移出，氮源气体流入处理室。然后在处理室中形成第二等离子体第二预定量的时间，其中以显着均匀的方式氮化基板。

4. 发明授权

US07227201B2 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US07227201B2
公开(公告)日：2007-06-05
申请号：US10927858
申请日：2004-08-27
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L27/10
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

5. 发明申请

US20060046514A1 Thermal treatment of nitrided oxide to improve negative bias thermal instability 有权
标题翻译：氮化氧化物的热处理以改善负偏压热不稳定性
公开(公告)号：US20060046514A1
公开(公告)日：2006-03-02
申请号：US10930230
申请日：2004-08-31
申请人： Husam Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy Chancellor , Anand Krishnan , Malcolm Bevan
发明人： Husam Alshareef , Rajesh Khamankar , Ajith Varghese , Cathy Chancellor , Anand Krishnan , Malcolm Bevan
IPC分类号： H01L21/31
CPC分类号： H01L21/02326 , H01L21/0214 , H01L21/02337 , H01L21/265 , H01L21/28202 , H01L21/3144 , H01L21/823857 , H01L29/518 , H01L29/7833
摘要： A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.
摘要翻译：一种降低在温度和电压应力之后导致的MOSFET晶体管的阈值电压偏移的方法，以及根据该方法制造的集成电路器件。该方法包括以下步骤：在半导体衬底上形成氮化介电层，并将氮化介电层在低压下进行退火。

6. 发明申请

US20070207572A1 CMOS Device Having Different Amounts of Nitrogen in the NMOS Gate Dielectric Layers and PMOS Gate Dielectric Layers 有权
标题翻译：在NMOS栅极电介质层和PMOS栅介质层中具有不同氮含量的CMOS器件
公开(公告)号：US20070207572A1
公开(公告)日：2007-09-06
申请号：US11745930
申请日：2007-05-08
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L21/82
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

7. 发明申请

US20060043369A1 CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers 有权
标题翻译： CMOS器件在NMOS栅极电介质层和PMOS栅极电介质层中具有不同量的氮
公开(公告)号：US20060043369A1
公开(公告)日：2006-03-02
申请号：US10927858
申请日：2004-08-27
申请人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
发明人： Ajith Varghese , Husam Alshareef , Rajesh Khamankar
IPC分类号： H01L29/76
CPC分类号： H01L21/28202 , H01L21/823857 , H01L29/513 , H01L29/518
摘要： The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
摘要翻译：本发明提供了一种互补金属氧化物半导体（CMOS）器件及其制造方法，以及包括该互补金属氧化物半导体器件的集成电路。在本发明的示例性实施例中，CMOS器件（100）包括具有第一栅极介电层（133）和位于第一栅极电极层（138）的p沟道金属氧化物半导体（PMOS）器件（120）在衬底（110）上，其中第一栅极电介质层（133）具有位于其中的一定量的氮。除了PMOS器件（120）之外，CMOS器件还包括具有第二栅极电介质层（173）和第二栅电极层（178）的n沟道金属氧化物半导体（NMOS）器件（160）衬底（110），其中所述第二栅极电介质层（173）具有位于其中的不同量的氮。因此，本发明允许对PMOS器件（120）和NMOS器件（160）的阈值电压进行单独调谐。

8. 发明申请

US20090045472A1 Methodology for Reducing Post Burn-In Vmin Drift 审中-公开
标题翻译：降低后燃烧Vmin漂移的方法
公开(公告)号：US20090045472A1
公开(公告)日：2009-02-19
申请号：US11837709
申请日：2007-08-13
申请人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
发明人： Srinivasan Chakravarthi , Narendra Singh Mehta , Rajesh Khamankar , Ajith Varghese , Malcolm J. Bevan , Tad Grider
IPC分类号： H01L29/94 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/28035 , H01L21/28176 , H01L29/4916 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device includes source/drain regions formed in a substrate and having a concentration of nitrogen of at least about 5E18 cm−3. A gate dielectric is located over the substrate and between the source/drain regions. Gate sidewall spacers are located over said source/drain regions. A nitrogen-doped electrode including polysilicon is located over the gate dielectric. The electrode has a concentration of nitrogen therein greater than the concentration of nitrogen in the source/drain regions.
摘要翻译：半导体器件包括形成在衬底中并具有至少约5E18cm-3的氮浓度的源极/漏极区域。栅极电介质位于衬底上并且在源/漏区之间。栅极侧壁间隔物位于所述源极/漏极区域之上。包括多晶硅的氮掺杂电极位于栅极电介质上方。电极的氮浓度大于源极/漏极区域中的氮浓度。

9. 发明申请

US20080076076A1 REWORK METHODOLOGY THAT PRESERVES GATE PERFORMANCE 审中-公开
标题翻译：保持门控性能的方法学
公开(公告)号：US20080076076A1
公开(公告)日：2008-03-27
申请号：US11534342
申请日：2006-09-22
申请人： Yaw Samuel Obeng , Yu-Tai Lee , Rajesh Khamankar , April Gurba , Brian Kirkpatrick , Ajith Varghese
发明人： Yaw Samuel Obeng , Yu-Tai Lee , Rajesh Khamankar , April Gurba , Brian Kirkpatrick , Ajith Varghese
IPC分类号： G03F7/26
CPC分类号： H01L21/0273 , G03F7/423 , G03F7/427
摘要： In one embodiment, a method of manufacturing an integrated circuit that comprises forming a circuit layer over a substrate, forming a resist layer on the circuit layer, and subjecting the resist layer to a rework process that includes exposing the resist layer to an organic wash. In another embodiment, the method of manufacturing an integrated circuit comprises forming a circuit layer over a substrate, forming a priming layer on the circuit layer, and subjecting the resist layer to the rework process. The reworking process includes exposing the substrate to a mild plasma ash to substantially remove portions of the resist layer but leave the priming layer.
摘要翻译：在一个实施例中，一种制造集成电路的方法包括在衬底上形成电路层，在电路层上形成抗蚀剂层，并对抗蚀剂层进行包括将抗蚀剂层暴露于有机洗涤物的返工工艺。在另一个实施例中，制造集成电路的方法包括在衬底上形成电路层，在电路层上形成起动层，并对抗蚀剂层进行返工处理。返修过程包括将基底暴露于温和的等离子体灰中以基本上去除抗蚀剂层的部分，但留下引发层。

10. 发明授权

US08119470B2 Mitigation of gate to contact capacitance in CMOS flow 有权
标题翻译：栅极接触电容在CMOS流中的缓解
公开(公告)号：US08119470B2
公开(公告)日：2012-02-21
申请号：US11726253
申请日：2007-03-21
申请人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
发明人： Shashank Sureshchandra Ekbote , Borna Obradovic , Lindsey Hall , Craig Huffman , Ajith Varghese
IPC分类号： H01L21/338 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7833 , H01L21/76804 , H01L21/76897 , H01L29/6656 , H01L29/6659 , Y02P80/30
摘要： Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.
摘要翻译：主要是氧化物而不是氮化物的侧壁间隔物邻近CMOS晶体管的栅极叠层形成。单独的侧壁间隔物位于栅极堆叠的导电栅电极和晶体管的导电接触之间。因此，取决于插入的侧壁间隔物的介电常数，可以在栅电极和接触之间产生电容。因此，从具有比氮化物更低的介电常数的氧化物形成侧壁间隔物减轻了另外可能在这些特征之间产生的电容。这种电容至少是不利的，因为它可以抑制晶体管的切换速度。因此，如本文所述的形成侧壁间隔件可以通过减少具有不令人满意的切换速度和/或其它不期望的性能特征的设备的数量来减轻产量损失。

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