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    • 4. 发明申请
    • High Efficiency Solar Cells and Manufacturing Methods
    • 高效太阳能电池和制造方法
    • US20080047601A1
    • 2008-02-28
    • US11841629
    • 2007-08-20
    • Somnath NagMehrdad Moslehi
    • Somnath NagMehrdad Moslehi
    • H01L31/04H01L21/00
    • H01L31/03529H01L31/07Y02E10/50
    • A Schottky contact photovoltaic energy conversion cell. The Schottky contact photovoltaic energy conversion cell comprises a flexible substrate and a first array of a plurality of closely-spaced microscale pillars connected to a first electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a first Schottky metal material with a work function selected for efficiently collecting photogenerated electrons. The Schottky contact photovoltaic energy conversion cell further comprises a second array of a plurality of closely-spaced microscale pillars connected to a second electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a second Schottky metal material with a work function selected for efficiently collecting photogenerated holes. The Schottky contact photovoltaic energy conversion cell further comprises a semiconductor absorber thin-film layer covering the first and second contacts and filling spaces among all the pillars, for creating photogenerated electrons and holes.
    • 肖特基接触光伏能量转换电池。 肖特基接触光伏能量转换单元包括柔性基板和连接到第一电单元接触件的多个紧密间隔的微米柱的第一阵列。 柱和接触由具有选择用于有效收集光生电子的功函数的第一肖特基金属材料(或具有顶部)层形成。 肖特基接触光伏能量转换单元还包括连接到第二电池触点的多个紧密间隔的微小柱的第二阵列。 支柱和接触由具有选择用于有效收集光生孔的功函数的(或具有顶部)第二肖特基金属材料层形成。 肖特基接触光伏能量转换单元还包括覆盖所有第一和第二触点和填充空间的半导体吸收体薄膜层,用于产生光生电子和空穴。
    • 6. 发明申请
    • SOLAR MODULE STRUCTURES AND ASSEMBLY METHODS FOR THREE-DIMENSIONAL THIN-FILM SOLAR CELLS
    • 太阳能模块结构和三维薄膜太阳能电池的组装方法
    • US20090301549A1
    • 2009-12-10
    • US11868491
    • 2007-10-06
    • Mehrdad Moslehi
    • Mehrdad Moslehi
    • H01L31/048H01L31/042H01L31/18
    • H01L31/0504H01L31/042H01L31/046H01L31/0463H01L31/048H01L31/05H01L31/056H01L31/18Y02B10/12Y02E10/50
    • Solar module structures 210 and 270 and methods for assembling solar module structures. The solar module structures 210 and 270 comprise three-dimensional thin-film solar cells 110 arranged in solar module structures 210 and 270. The three-dimensional thin-film solar cell comprises a three-dimensional thin-film solar cell substrate (124 and 122, respectively) with emitter junction regions 1352 and doped base regions 1360. The three-dimensional thin-film solar cell further includes emitter metallization regions and base metallization regions. The 3-D TFSC substrate comprises a plurality of single-aperture or dual-aperture unit cells. The solar module structures 270 using three-dimensional thin-film solar cells comprising three-dimensional thin-film solar cell substrates with a plurality of dual-aperture unit cells may be used in solar glass applications. The solar module structures 210 using three-dimensional thin-film solar cells comprising three-dimensional thin-film solar cell substrates with a plurality of single-aperture unit cells may be used in building façade and rooftop installation applications as well as for centralized solar electricity generation.
    • 太阳能模块结构210和270以及用于组装太阳能模块结构的方法。 太阳能模块结构210和270包括布置在太阳能模块结构210和270中的三维薄膜太阳能电池110.三维薄膜太阳能电池包括三维薄膜太阳能电池基板(124和122 ,分别具有发射极结区域1352和掺杂基极区域1360.三维薄膜太阳能电池还包括发射极金属化区域和基底金属化区域。 3-D TFSC基板包括多个单孔或双孔单元电池。 使用包括具有多个双孔单元电池的三维薄膜太阳能电池基板的三维薄膜太阳能电池的太阳能模块结构270可以用于太阳能玻璃应用中。 使用包括具有多个单孔单元电池的三维薄膜太阳能电池基板的三维薄膜太阳能电池的太阳能模块结构210可以用于建筑立面和屋顶安装应用以及集中式太阳能发电 代。
    • 7. 发明授权
    • Self-aligned silicide process
    • 自对准硅化物工艺
    • US5322809A
    • 1994-06-21
    • US60774
    • 1993-05-11
    • Mehrdad Moslehi
    • Mehrdad Moslehi
    • H01L21/28H01L21/285H01L21/336H01L29/78H01L21/283
    • H01L29/66507H01L21/28518H01L29/6659H01L29/66545Y10S148/019Y10S148/147
    • A self-aligned silicide process that enables different silicide thicknesses for polysilicon gates and source/drain junction regions. Semiconductor body (10) includes a doped well (14) formed in substrate (12). Field insulating region (18) is located above channel stop region (16) in doped well (14). Implanted within doped well (14) are source/drain junctions (34). Source/drain junctions (34) are shallow heavily doped regions. The surfaces of source/drain junctions (34) are silicided. Silicide gate (44) is separated from the surface of doped well (14) by gate insulator layer (20) and contains a silicide layer (40) and a doped polysilicon layer (22). The thickness of silicide layer (40) is not limited by the thickness of the silicided surfaces of source/drain junctions (34) or the amount of silicon consumed over these junctions. Silicon nitride sidewall spacers (32) separate the sidewall edges of silicide gate (44) and the transistor channel region from the source/drain junction silicide layer 41.
    • 自对准硅化物工艺,其能够实现多晶硅栅极和源极/漏极结区域的不同硅化物厚度。 半导体本体(10)包括形成在衬底(12)中的掺杂阱(14)。 场绝缘区域(18)位于掺杂阱(14)中的通道停止区域(16)的上方。 掺杂在掺杂阱(14)内的是源极/漏极结(34)。 源极/漏极结(34)是浅重掺杂区域。 源极/漏极结(34)的表面被硅化。 硅化物栅极(44)通过栅极绝缘体层(20)与掺杂阱(14)的表面分离,并且包含硅化物层(40)和掺杂多晶硅层(22)。 硅化物层(40)的厚度不受源极/漏极结(34)的硅化物表面的厚度或在这些结上消耗的硅的量的限制。 氮化硅侧壁间隔件(32)将硅化物栅极(44)的侧壁边缘和晶体管沟道区域与源极/漏极结硅化物层41分离。