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1. 发明授权

US06645847B2 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06645847B2
公开(公告)日：2003-11-11
申请号：US10060548
申请日：2002-01-30
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

2. 发明授权

US06627995B2 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06627995B2
公开(公告)日：2003-09-30
申请号：US10113191
申请日：2002-04-01
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L2348
CPC分类号： H01L21/76864 , H01L21/28556 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76862 , H01L21/76876 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

3. 发明授权

US06365502B1 Microelectronic interconnect material with adhesion promotion layer and fabrication method 失效
公开(公告)号：US06365502B1
公开(公告)日：2002-04-02
申请号：US09518294
申请日：2000-03-03
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Boris Relja , Randhir S. Bubber , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , David M. Leet , Sanjay Gopinath
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

4. 发明授权

US06461675B2 Method for forming a copper film on a substrate 失效
标题翻译：在基板上形成铜膜的方法
公开(公告)号：US06461675B2
公开(公告)日：2002-10-08
申请号：US09113852
申请日：1998-07-10
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , Zeming Liu , Guihua Shang
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Lino A. Velo , Thomas R. Omstead , David R. Campbell, Sr. , Zeming Liu , Guihua Shang
IPC分类号： C23C1606
CPC分类号： H01L21/76858 , C23C16/0209 , C23C16/0245 , C23C16/0281 , C23C16/18 , H01L21/76843 , H01L21/76862 , H01L21/76876 , H01L21/76877 , H01L2221/1089
摘要： Adhesion of a copper film, such as a copper interconnect, to a substrate underlayer, such as a substrate diffusion barrier, is enhanced with adhesion promotion techniques. The adhesion promotion techniques can repair the interface of the copper film and the substrate to enhance adhesion of the copper film for high-yield formation of inlaid copper metal lines and plugs. For instance, thermal annealing of a seed layer, including a copper seed layer, an alloy seed layer or a reactant seed layer, can repair contamination at the interface of the seed layer and the substrate. Alternatively, the adhesion promotion techniques can avoid contamination of the interface by depositing an inert seed layer, such as a noble (e.g., platinum) or passivated metal seed layer, or by depositing the seed layer under predetermined conditions that minimize contamination of the interface, and then depositing a bulk copper layer under predetermined conditions that maximize throughput. Alternatively, the adhesion promotion techniques can avoid the formation of an interface by graduated deposition of a first material and copper.
摘要翻译：通过粘合促进技术增强铜膜如铜互连对衬底底层（例如衬底扩散阻挡层）的粘合性。粘合促进技术可以修复铜膜和基材的界面，以增强铜膜的粘附性，从而高收率地形成嵌入的铜金属线和插塞。例如，种子层（包括铜籽晶层，合金种子层或反应物种子层）的热退火可以修复种子层和基底的界面处的污染。或者，粘合促进技术可以避免通过沉积惰性种子层（例如贵金属（例如铂）或钝化金属种子层）或通过在限制界面的污染最小化的预定条件下沉积籽晶层来污染界面，然后在允许生产量最大化的预定条件下沉积大块铜层。或者，粘合促进技术可以避免通过第一材料和铜的分级沉积形成界面。

5. 发明授权

US06444263B1 Method of chemical-vapor deposition of a material 失效
标题翻译：化学气相沉积材料的方法
公开(公告)号：US06444263B1
公开(公告)日：2002-09-03
申请号：US09663209
申请日：2000-09-15
申请人： Ajit P. Paranjpe , Randhir S. Bubber , Sanjay Gopinath , Thomas R. Omstead , Mehrdad M. Moslehi
发明人： Ajit P. Paranjpe , Randhir S. Bubber , Sanjay Gopinath , Thomas R. Omstead , Mehrdad M. Moslehi
IPC分类号： C23C1616
CPC分类号： C23C16/16 , C23C16/0281
摘要： A method for chemical-vapor deposition of a material film adds precursor decomposition by-product to the precursor flow to suppress premature gas-phase precursor decomposition and improve process repeatability and film quality. In one embodiment, CVD cobalt films are deposited with carbonyl precursors with reduced premature gas-phase reaction and particulate generation by the addition of excess carbon monoxide to the process chamber comprising the precursor flow. The addition of carbon monoxide not only suppresses gas-phase reaction but also improves cobalt film purity. The addition of excess carbon monoxide to CVD cobalt precursor flow provides repeatable deposition of glue and nucleation layers to support CVD copper, and is extendable to the deposition of high purity CVD cobalt for other applications and with other precursors, and also extendable for CVD CoSi2 films and other cobalt-containing applications.
摘要翻译：材料膜的化学气相沉积方法将前体分解副产物添加到前体流中以抑制过早气相前体分解，并提高工艺重复性和膜质量。在一个实施方案中，通过在包含前体流的处理室中加入过量的一氧化碳，将CVD钴膜沉积在羰基前体中，同时减少过早的气相反应和颗粒产生。加入一氧化碳不仅抑制了气相反应，而且还提高了钴膜的纯度。过量的一氧化碳添加到CVD钴前体流中提供了可重复沉积的胶和成核层以支持CVD铜，并且可扩展到用于其它应用和其它前体的高纯度CVD钴的沉积，并且还可用于CVD CoSi 2膜和其他含钴应用。

6. 发明授权

US06294836B1 Semiconductor chip interconnect barrier material and fabrication method 失效
标题翻译：半导体芯片互连屏障材料及制造方法
公开(公告)号：US06294836B1
公开(公告)日：2001-09-25
申请号：US09219147
申请日：1998-12-22
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
摘要翻译：微电子半导体互连结构屏障和沉积方法为高性能器件互连提供改进的导电阻挡材料性质。阻挡层包括选自铂，钯，铱，铑和锡的掺杂剂。阻挡层可以包括选自钽，钨钛，铬和钴的难熔金属，并且还可以包括选自碳，氧和氮的第三元素。通过化学气相沉积可以通过化学气相沉积来沉积掺杂剂和其它阻挡材料以实现良好的阶梯覆盖，并且在一个实施例中，具有良好成核表面的相对适形的薄膜用于随后的金属化，例如铜金属化，屏障抑制铜扩散到其它层的器件，包括金属间电介质，预金属电介质和晶体管结构。

7. 发明授权

US06812126B1 Method for fabricating a semiconductor chip interconnect 失效
标题翻译：半导体芯片互连的制造方法
公开(公告)号：US06812126B1
公开(公告)日：2004-11-02
申请号：US09553933
申请日：2000-04-21
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/2855 , H01L21/28556 , H01L21/28568 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and time. The barrier can comprises a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
摘要翻译：微电子半导体互连结构屏障和沉积方法为高性能器件互连提供改进的导电阻挡材料性质。阻挡层包括选自铂，钯，铱，铑和时间的掺杂剂。阻挡层可以包括选自钽，钨钛，铬和钴的难熔金属，并且还可以包含选自碳，氧和氮的第三元素。可以通过化学气相沉积来沉积掺杂剂和其它阻挡材料以实现良好的阶梯覆盖，并且具有良好成核表面的相对适形的薄膜用于随后的金属化，例如铜金属化。在一个实施例中，屏障抑制铜扩散到器件的其它层，包括金属间电介质，预金属电介质和晶体管结构。

8. 发明授权

US06204204B1 Method and apparatus for depositing tantalum-based thin films with organmetallic precursor 失效
标题翻译：用有机金属前体沉积钽基薄膜的方法和设备
公开(公告)号：US06204204B1
公开(公告)日：2001-03-20
申请号：US09282952
申请日：1999-04-01
申请人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
发明人： Ajit P. Paranjpe , Mehrdad M. Moslehi , Randhir S. Bubber , Lino A. Velo
IPC分类号： H01L21302
CPC分类号： H01L21/76862 , C23C16/34 , C23C16/448 , H01L21/28556 , H01L21/76843
摘要： A method and apparatus are disclosed for depositing a tantalum-containing diffusion barrier, such as a TaN barrier layer, by dissolving a tantalum-bearing organometallic precursor, such as PEMAT or PDEAT, in an inert, low viscosity, high molecular weight, low volatility solvent, such as octane, heptane, decane or toluene. The precursor-solvent solution is vaporized and flowed over a substrate to deposit the barrier. The precursor solution has a viscosity substantially similar to that of the solvent by maintaining the ratio of precursor to solvent at a generally low value, such as approximately 10% precursor. The boiling point of the solvent is substantially similar to the boiling point of the precursor, such as within 50% of the precursor boiling point at one atmosphere, to enhance repeatability of barrier film quality. Resistivity of the barrier film is reduced by flowing a reactive gas with the precursor flow, the reactive gas reducing the carbon content of the barrier film, or by co-deposition of a resistivity-lowering metallic dopant with the precursor solution. Alternatively, resistivity is reduced by controlling the nitrogen content of the film by a post-deposition plasma treatment of the barrier with a reducing gas.
摘要翻译：公开了一种方法和装置，用于通过将含钽的有机金属前体如PEMAT或PDEAT溶解在惰性，低粘度，高分子量，低挥发性中来沉积含钽的扩散阻挡层，例如TaN阻挡层溶剂，如辛烷，庚烷，癸烷或甲苯。前体溶剂溶液蒸发并流过基底以沉积屏障。通过将前体与溶剂的比例保持在通常较低的值，例如约10％的前体，前体溶液具有与溶剂基本相似的粘度。溶剂的沸点基本上类似于前体的沸点，例如在一个大气压下的前体沸点的50％以内，以提高阻挡膜质量的重复性。阻挡膜的电阻率通过使与前体流反应的气体流动，反应气体降低阻挡膜的碳含量，或通过与前体溶液共沉积电阻率降低金属掺杂剂来降低。或者，通过用还原气体对阻挡层进行后期等离子体处理来控制膜的氮含量来降低电阻率。

9. 发明授权

US5326170A Wireless temperature calibration device and method 失效
标题翻译：无线温度校准装置及方法
公开(公告)号：US5326170A
公开(公告)日：1994-07-05
申请号：US115920
申请日：1993-09-01
申请人： Mehrdad M. Moslehi , Habib Najm , Lino A. Velo
发明人： Mehrdad M. Moslehi , Habib Najm , Lino A. Velo
IPC分类号： G01K15/00 , G01J5/00 , G01J5/52 , H01L21/26 , H01L21/324 , H01L21/66 , G01J5/54
CPC分类号： G01K15/005 , G01J5/522 , G01J2005/0048
摘要： A method for calibrating at least one temperature sensor. A wafer (30) having calibration structures of a material having a melting point in the range of 150.degree. to 1150.degree. C. is provided. The temperature sensor is operable to detect a temperature dependent characteristic of the wafer and output a signal corresponding to the temperature depending characteristic. The power input is selectively varied and the wafer temperature is ramped for a calibration run. A wafer characteristic, such as wafer reflectance, radiance, or emissivity, is monitored. A first step change in the wafer characteristic corresponding to a wafer temperature equal to the melting point of the calibration structures is detected and a set of calibration parameters for each temperature sensor being calibrated is calculated.
摘要翻译：一种用于校准至少一个温度传感器的方法。提供具有熔点在150〜1150℃范围内的材料的校准结构的晶片（30）。温度传感器可操作以检测晶片的温度依赖特性并输出对应于温度依赖特性的信号。功率输入有选择地变化，并且晶片温度斜坡进行校准运行。监测诸如晶片反射率，辐射度或发射率的晶片特性。检测对应于等于校准结构的熔点的晶片温度的晶片特性的第一阶跃变化，并计算正在校准的每个温度传感器的一组校准参数。

10. 发明授权

US5305417A Apparatus and method for determining wafer temperature using pyrometry 失效
标题翻译：使用高温计测定晶片温度的装置和方法
公开(公告)号：US5305417A
公开(公告)日：1994-04-19
申请号：US37771
申请日：1993-03-26
申请人： Habib N. Najm , Mehrdad M. Moslehi , Somnath Banerjee , Lino A. Velo
发明人： Habib N. Najm , Mehrdad M. Moslehi , Somnath Banerjee , Lino A. Velo
IPC分类号： G01J5/10 , C30B25/10 , G01J5/08 , G05D23/19 , G05D23/27 , H01L21/66 , G01J5/06
CPC分类号： B24B37/013 , C30B25/10 , G05D23/27 , H01L22/26 , H01L22/12
摘要： In a RTP reactor where wafer temperature is measured by a pyrometer assembly (32), a pyrometer assembly (50) is further provided to measure the temperature of the quartz window (30) that is situated between the wafer pyrometer assembly (32) and the wafer (16) that is being processed. During the calibration procedure (100, 120) where a thermocouple wafer is used, the measurements from the wafer pyrometer assembly (32) and the window pyrometer assembly (50) are calibrated, and pyrometer measurements and thermocouple measurements are collected and compiled into calibration tables. During actual RTP reactor operation, the data from the calibration tables and current wafer and window pyrometer measurements are used to compute corrected wafer temperature(s). The corrected wafer temperature(s) is/are then used to control the intensities of the heating lamps according to the wafer processing heating schedule.
摘要翻译：在通过高温计组件（32）测量晶片温度的RTP反应器中，还提供高温计组件（50）以测量位于晶片高温计组件（32）和晶片高温计组件（32）之间的石英窗口（30）的温度，正在处理的晶片（16）。在使用热电偶晶片的校准过程（100,120）期间，对来自晶片高温计组件（32）和窗口高温计组件（50）的测量进行校准，并将高温计测量和热电偶测量值收集并编译成校准表。在实际的RTP电抗器操作期间，使用来自校准表和当前晶圆和窗口高温计测量的数据来计算校正的晶片温度。然后使用校正的晶片温度来根据晶片加工时间表来控制加热灯的强度。

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