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1. 发明授权

US07243324B2 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US07243324B2
公开(公告)日：2007-07-10
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

2. 发明申请

US20050010884A1 Optimizing IC clock structures by minimizing clock uncertainty 有权
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US20050010884A1
公开(公告)日：2005-01-13
申请号：US10616623
申请日：2003-07-10
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G01R31/30 , G06F1/10 , G06F9/45
CPC分类号： G06F1/10 , G01R31/3016
摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined character along the first path. A second path from the launching cell toward the clock source is back-traced to a predetermined marked cell. Clock uncertainty is calculated based on the portion of the first path from the predetermined marked cell to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.
摘要翻译：通过从接收单元向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定字符的每个单元来估计接收小区和网络的启动小区之间的时钟不确定性。从启动单元向时钟源的第二条路径被追溯到预定的标记单元。基于从预定标记小区到接收小区的第一路径的部分来计算时钟不确定性。如果松弛不超过余量值，则计算时钟不确定度。在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。

3. 发明申请

US20060190886A1 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US20060190886A1
公开(公告)日：2006-08-24
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶的树形式的时钟网的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到该集合的重心的第二缓冲区。

4. 发明授权

US07356785B2 Optimizing IC clock structures by minimizing clock uncertainty 失效
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07356785B2
公开(公告)日：2008-04-08
申请号：US11402146
申请日：2006-04-11
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F1/10 , G01R31/3016
摘要： A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
摘要翻译：提供了一种用于优化具有由驱动器引脚限定的根和由驱动引脚限定的多个叶片的树形式的时钟网络的过程。该过程包括将第一缓冲区强制到多个叶片的重心，插入一组第二缓冲器，使得每个叶片被插入的缓冲器驱动而没有定时违反，并且将第一缓冲器移动到集合的重心的第二缓冲区。

5. 发明申请

US20060190901A1 Method of buffer insertion to achieve pin specific delays 有权
标题翻译：缓冲区插入方式来实现引脚特定的延迟
公开(公告)号：US20060190901A1
公开(公告)日：2006-08-24
申请号：US11041489
申请日：2005-01-24
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as output a revised integrated circuit design that includes the buffer sub-tree.
摘要翻译：一种用于集成电路设计中的树形网络的缓冲器插入方法包括以下步骤：（a）接收作为输入的包括树形网络的集成电路设计; （b）从单元库选择可用于集成电路设计的缓冲器类型，其导致预定导线长度的最小总延迟; （c）识别树网络中具有所需针特定目标延迟的候选叶节点; （d）在由候选叶节点到树网络的根节点的路径穿过的每个内部节点之间插入缓冲器，并且不是候选叶节点的每个叶节点; （e）从由候选叶节点到树网络的根节点的路径遍历的每个内部节点的上游内部节点在树形网络中创建缓冲器子树; 将通过从候选叶节点到树树网络的根节点的路径遍历的每个内部节点重新编入缓冲器子树中的新缓冲器; 和（g）产生包括缓冲器子树的经修订的集成电路设计的输出。

6. 发明授权

US07096442B2 Optimizing IC clock structures by minimizing clock uncertainty 有权
标题翻译：通过最小化时钟不确定性优化IC时钟结构
公开(公告)号：US07096442B2
公开(公告)日：2006-08-22
申请号：US10616623
申请日：2003-07-10
申请人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
发明人： Aiguo Lu , Ivan Pavisic , Nikola Radovanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F1/10 , G01R31/3016
摘要： Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined characteristic along the first path. A second path from the launching cell toward the clock source is back-traced to a common one of the marked cells having the predetermined characteristic. Clock uncertainty is calculated based on the portion of the first path from the common marked cell having the predetermined characteristic to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.
摘要翻译：通过从接收小区向时钟源的后向跟踪第一路径并且沿着第一路径标记具有预定特性的每个小区来估计接收小区和网络的启动小区之间的时钟不确定性。从发射单元朝向时钟源的第二路径被追溯到具有预定特性的标记单元中的共同的一个。基于从具有预定特征的公共标记小区到接收小区的第一路径的部分来计算时钟不确定性。如果松弛不超过余量值，则计算时钟不确定度。在一个实施例中，通过将第一缓冲器强制为具有网络的多个缓冲器的重心而没有定时违反来最大化从根到强制缓冲器的公共路径，使得最小化从强制缓冲区到叶片的非公共路径，从而最小化时钟不确定性。

7. 发明授权

US08239813B2 Method and apparatus for balancing signal delay skew 失效
标题翻译：信号延迟偏移平衡的方法和装置
公开(公告)号：US08239813B2
公开(公告)日：2012-08-07
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykih , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

8. 发明授权

US06470487B1 Parallelization of resynthesis 有权
标题翻译：再合成平行化
公开(公告)号：US06470487B1
公开(公告)日：2002-10-22
申请号：US09842350
申请日：2001-04-25
申请人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
发明人： Andrej A. Zolotykh , Elyar E. Gasanov , Ivan Pavisic , Aiguo Lu
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A method for resynthesizing a design of an integrated circuit using a parallel processing mode. A single processing mode is entered by activating a main thread and locking a semaphore associated with the main thread. The design of the integrated circuit is resynthesized using the main thread. Tasks to be accomplished in the parallel processing mode are identified. The semaphore associated with the main thread is unlocked, and the operation of the single processing mode is ceased. Ordinal threads are activated by unlocking a semaphore associated with each ordinal thread. The tasks are processed in parallel by assigning the tasks to the ordinal threads and the main thread. Upon completion of one of the assigned tasks by one of the ordinal threads, it is determined whether an additional task remains to be assigned. In the case where the additional task remains, the additional task is assigned to the completed one of the ordinal threads. In the case where the additional task does not remain, the completed one of the ordinal threads is inactivated. Upon inactivation of all of the ordinal threads, a return is made to the single processing mode, with the ordinal threads remaining inactive unless and until the main thread identifies more tasks to be accomplished in the parallel processing mode.
摘要翻译：一种使用并行处理模式重新合成集成电路的设计的方法。通过激活主线程并锁定与主线程相关联的信号量来输入单个处理模式。集成电路的设计使用主线重新合成。识别以并行处理模式完成的任务。与主线程相关联的信号量被解锁，并且停止单处理模式的操作。通过解锁与每个顺序线程相关联的信号量激活有序线程。通过将任务分配给顺序线程和主线程，并行处理任务。在通过其中一个顺序线程完成一个分配的任务之后，确定是否还有一个额外的任务被分配。在附加任务保留的情况下，附加任务被分配给完成的一个序数线程。在附加任务不存在的情况下，完成的一个顺序线程将被禁用。在所有顺序线程失效后，返回到单个处理模式，顺序线程保持不活动，除非主线程在并行处理模式下识别要完成的更多任务。

9. 发明申请

US20110258587A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 失效
标题翻译：信号延迟减少系统
公开(公告)号：US20110258587A1
公开(公告)日：2011-10-20
申请号：US13173855
申请日：2011-06-30
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system and method are provided for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist having components and connection paths among the components; identifying a first connection path in the initial netlist that comprises path fragments for which there are no equivalent path fragments in a second connection path in the initial netlist; generating a skew-corrected netlist wherein the second connection path is re-routed to have path fragments equivalent to the path fragments of the first connection path; and outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，提供了一种用于减少信号延迟偏差的系统和方法。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括：接收在组件之间具有组件和连接路径的初始网表; 识别所述初始网表中的第一连接路径，其包括在所述初始网表中的第二连接路径中不存在等效路径片段的路径片段; 生成偏差校正网表，其中所述第二连接路径被重新路由以具有等同于所述第一连接路径的路径片段的路径片段; 并输出偏差校正的网表。

10. 发明申请

US20090187873A1 SIGNAL DELAY SKEW REDUCTION SYSTEM 有权
标题翻译：信号延迟减少系统
公开(公告)号：US20090187873A1
公开(公告)日：2009-07-23
申请号：US12015925
申请日：2008-01-17
申请人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
发明人： Andrey Nikitin , Ranko Scepanovic , Igor Kucherenko , William Lau , Cheng-Gang Kong , Hui-Yin Seto , Andrej Zolotykh , Ivan Pavisic , Sandeep Bhutani , Aiguo Lu , Ilya Lyalin
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/84
摘要： A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.
摘要翻译：根据各种实施例，公开了一种用于减小信号延迟偏差的系统。本公开的一个说明性实施例涉及一种方法。根据一个说明性实施例，该方法包括接收包括组件之间的组件和连接路径的初始网表。该方法还包括识别在初始网表中的第一连接路径中的一个或多个偏斜影响特征，其在初始网表中的第二连接路径中缺少对应的偏斜影响特征。该方法还包括生成偏差校正网表，其中第二连接路径包括与第一连接路径的相应的一个或多个相加的偏斜影响特征。该方法还包括输出经偏斜校正的网表。

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