专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP1207623B1 Gated clock recovery circuit 有权
标题翻译：时钟恢复电路交换
公开(公告)号：EP1207623B1
公开(公告)日：2009-08-12
申请号：EP01309756.3
申请日：2001-11-20
申请人： Agere Systems Guardian Corporation
发明人： Dunlop, Alfred Earl , Fischer, Wilhelm Carl
IPC分类号： H03L7/07 , H04L7/033
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/14 , H04L7/0004 , H04L7/033

2. 发明公开

EP1207623A2 Gated clock recovery circuit 有权
标题翻译： Geschaltete Schaltung zurTaktrückgewinnung
公开(公告)号：EP1207623A2
公开(公告)日：2002-05-22
申请号：EP01309756.3
申请日：2001-11-20
申请人： Agere Systems Guardian Corporation
发明人： Dunlop, Alfred Earl , Fischer, Wilhelm Carl
IPC分类号： H03L7/07 , H04L7/033
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL1) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP1, to the second PLL (PLL2) to indirectly initially tune the second PLL. The bias voltage, CAP1, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP2, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP2, is removed and the second PLL can operate without being controlled by PLL1 so that the second PLL oscillates in phase with the received data. Simultaneously, the received data starts the oscillator in the second PLL so that the second oscillator is in phase with the received data. The second PLL then maintains this phase relationship between the second oscillator and the received data.
摘要翻译：公开了一种门控时钟恢复电路，其接收输入数据流并产生频率和相位对准的时钟输出。门控时钟恢复电路基本上瞬时地调整所生成的时钟信号以输入数据流中的相位变化。此外，门控时钟恢复电路仅使用所发送的非预定数据来产生时钟输出信号。门控时钟恢复电路包括两个PLL电路。第一个PLL（PLL1）根据发射机的频率进行调整，并向第二个PLL（PLL2）提供偏置电压CAP1，以间接初始调谐第二个PLL。偏置电压CAP1通过最初处于闭合（短路）位置的传输门（或开关）施加到第二PLL。因此，第一PLL驱动第二PLL的偏置电压CAP2，使频率与发射机对齐，直到接收的数据打开传输门。此后，偏移电压CAP2被去除，并且第二PLL可以在不被PLL1控制的情况下操作，使得第二PLL与接收到的数据同相地振荡。同时，所接收的数据在第二PLL中启动振荡器，使得第二振荡器与所接收的数据同相。第二PLL然后保持第二振荡器和接收到的数据之间的相位关系。

3. 发明公开

EP1207623A3 Gated clock recovery circuit 有权
标题翻译：时钟恢复电路交换
公开(公告)号：EP1207623A3
公开(公告)日：2004-11-17
申请号：EP01309756.3
申请日：2001-11-20
申请人： Agere Systems Guardian Corporation
发明人： Dunlop, Alfred Earl , Fischer, Wilhelm Carl
IPC分类号： H03L7/07 , H04L7/033
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/14 , H04L7/0004 , H04L7/033
摘要： A gated clock recovery circuit is disclosed that receives an input data stream and generates a frequency and phase aligned clock output. The gated clock recovery circuit substantially instantaneously adjusts the generated clock signal to phase changes in the incoming data stream. In addition, the gated clock recovery circuit generates the clock output signal using only transmitted non-predetermined data. The gated clock recovery circuit includes two PLL circuits. The first PLL (PLL1) adjusts to the frequency of the transmitter, and provides a bias voltage, CAP1, to the second PLL (PLL2) to indirectly initially tune the second PLL. The bias voltage, CAP1, is applied to the second PLL through a transmission gate (or switch) that is initially in a closed (short) position. Thus, the first PLL drives the bias voltage, CAP2, of the second PLL, to align the frequency with the transmitter, until received data opens the transmission gate. Thereafter, the bias voltage, CAP2, is removed and the second PLL can operate without being controlled by PLL1 so that the second PLL oscillates in phase with the received data. Simultaneously, the received data starts the oscillator in the second PLL so that the second oscillator is in phase with the received data. The second PLL then maintains this phase relationship between the second oscillator and the received data.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式