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1. 发明授权

US07633288B2 Method of testing semiconductor devices and handler used for testing semiconductor devices 有权
标题翻译：用于测试半导体器件的半导体器件和处理器的测试方法
公开(公告)号：US07633288B2
公开(公告)日：2009-12-15
申请号：US11527378
申请日：2006-09-27
申请人： Ae-Yong Chung , Eun-Seok Lee , Ki-Sang Kang , Kyeong-Seon Shin
发明人： Ae-Yong Chung , Eun-Seok Lee , Ki-Sang Kang , Kyeong-Seon Shin
IPC分类号： G01R31/28 , G01R31/26
CPC分类号： G01R31/2893
摘要： Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.
摘要翻译：示例性实施例可以提供通过识别批量单元和测试托盘来测试半导体器件的方法，使得具有半导体器件的多个批次可以由处理器连续测试。示例性实施例还可以提供用于测试半导体器件的处理器。

2. 发明申请

US20070075719A1 Method of testing semiconductor devices and handler used for testing semiconductor devices 有权
标题翻译：用于测试半导体器件的半导体器件和处理器的测试方法
公开(公告)号：US20070075719A1
公开(公告)日：2007-04-05
申请号：US11527378
申请日：2006-09-27
申请人： Ae-Yong Chung , Eun-Seok Lee , Ki-Sang Kang , Kyeong-Seon Shin
发明人： Ae-Yong Chung , Eun-Seok Lee , Ki-Sang Kang , Kyeong-Seon Shin
IPC分类号： G01R31/26
CPC分类号： G01R31/2893
摘要： Example embodiments may provide a method of testing semiconductor devices by identifying units of lots and a test tray such that a plurality of lots having semiconductor devices may be continuously tested by a handler. Example embodiments may also provide a handler used to test the semiconductor devices.
摘要翻译：示例性实施例可以提供通过识别批量单元和测试托盘来测试半导体器件的方法，使得具有半导体器件的多个批次可以由处理器连续测试。示例性实施例还可以提供用于测试半导体器件的处理器。

3. 发明申请

US20060158211A1 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US20060158211A1
公开(公告)日：2006-07-20
申请号：US11252448
申请日：2005-10-17
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/26
CPC分类号： G01R31/31926 , G01R31/31907
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

4. 发明授权

US07408339B2 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US07408339B2
公开(公告)日：2008-08-05
申请号：US11749053
申请日：2007-05-15
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/2893 , G01R31/2894 , G01R31/31718 , G01R31/31919
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过测试者和处理者之间的GPIB通信电缆发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

5. 发明授权

US07230417B2 Test system of semiconductor device having a handler remote control and method of operating the same 有权
标题翻译：具有处理器遥控器的半导体器件的测试系统及其操作方法
公开(公告)号：US07230417B2
公开(公告)日：2007-06-12
申请号：US11252448
申请日：2005-10-17
申请人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
发明人： Ae-Yong Chung , Eun-Seok Lee , Jeong-Ho Bang , Kyeong-Seon Shin , Dae-Gab Chi , Sung-Ok Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/31926 , G01R31/31907
摘要： A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.
摘要翻译：提供了一种用于处理器遥控器的半导体器件的测试系统。该系统包括：用于测试半导体器件的测试仪; 通过GPIB（通用指令总线）通信电缆连接到测试仪的处理器; 连接到测试器的测试仪服务器向测试者下载测试程序，处理程序遥控程序和处理程序状态检查程序; 以及通过GPIB通信电缆在测试者和处理者之间发送和接收的通信数据，其中通信数据具有用于半导体器件的电气测试的基本通信数据，用于处理器远程控制的通信数据和用于处理器状态的通信数据检查。

6. 发明授权

US06903567B2 Test apparatus having multiple test sites at one handler and its test method 有权
公开(公告)号：US06903567B2
公开(公告)日：2005-06-07
申请号：US10672994
申请日：2003-09-25
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/01 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

7. 发明授权

US07602172B2 Test apparatus having multiple head boards at one handler and its test method 有权
标题翻译：在一个处理机上具有多个头板的测试装置及其测试方法
公开(公告)号：US07602172B2
公开(公告)日：2009-10-13
申请号：US12109299
申请日：2008-04-24
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

8. 发明授权

US07378864B2 Test apparatus having multiple test sites at one handler and its test method 有权
标题翻译：在一个处理机上具有多个测试点的测试设备及其测试方法
公开(公告)号：US07378864B2
公开(公告)日：2008-05-27
申请号：US11092067
申请日：2005-03-28
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

9. 发明申请

US20050168236A1 Test apparatus having multiple test sites at one handler and its test method 有权
标题翻译：在一个处理机上具有多个测试点的测试装置及其测试方法
公开(公告)号：US20050168236A1
公开(公告)日：2005-08-04
申请号：US11092067
申请日：2005-03-28
申请人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
发明人： Ae-Yong Chung , Sung-Ok Kim , Kyeong-Seon Shin , Jeong-Ho Bang
IPC分类号： G01R31/26 , G01R31/01 , G01R31/28
CPC分类号： G01R31/2893 , G01R31/01 , G01R31/2851
摘要： A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.
摘要翻译：测试装置包括连接到测试器的一个处理器和分成两个或更多个站点或两个或更多个测试板的一个测试板。由于只有测试板（或测试板）上的站点需要复制，而不是处理器的加载通道或分拣机，所以测试设备可以方便地紧凑。此外，在一个站点或一个测试板上测试半导体器件时，可以根据测试结果对另一个站点中的另一个站点或另一个测试板上的半导体器件进行分类。这使得能够减少或消除测试器空闲时间以优化测试设备的效率。

10. 发明授权

US06972612B2 Semiconductor device with malfunction control circuit and controlling method thereof 有权
标题翻译：具有故障控制电路的半导体器件及其控制方法
公开(公告)号：US06972612B2
公开(公告)日：2005-12-06
申请号：US10277573
申请日：2002-10-21
申请人： Sang-Seok Kang , Kyeong-Seon Shin , Ki-Sang Kang
发明人： Sang-Seok Kang , Kyeong-Seon Shin , Ki-Sang Kang
IPC分类号： G01R31/30 , G11C17/18 , G11C29/00 , H01L23/544 , H01H37/76 , H01H85/00
CPC分类号： G01R31/30 , G11C17/18 , G11C29/006 , G11C2029/4402 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut. Then the discrimination signal is applied to the chip internal function circuits, to inhibit their operation if the fuse has been cut.
摘要翻译：半导体器件的集成电路具有嵌入芯片中的芯片故障控制电路。该电路包括一个定影部分，根据鉴别芯片中的缺陷的结果，在制造过程中将进行切割，其一端连接到第一电源端子。信号产生部分连接到定影部分的另一端，并连接到第二电源端子。信号产生部分通过定影部分是否被切断来产生鉴别芯片是否有故障的鉴别信号。鉴别信号被提供给至少一个内部功能电路，并且如果定影部件被切割，则禁止其操作。此外，芯片故障控制方法包括：如果测试保险丝已被切断，则产生具有第一状态的判别信号，如果测试保险丝未被切断，则产生第二状态。然后，识别信号被施加到芯片内部功能电路，如果保险丝被切断，则抑制它们的操作。

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