专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2022093428A1 REFRESHING DISPLAYS USING ON-DIE CACHE 审中-公开
公开(公告)号：WO2022093428A1
公开(公告)日：2022-05-05
申请号：PCT/US2021/051084
申请日：2021-09-20
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： JAIN, Ashish , PARTAP SINGH RANA, Dhirendra , NAFFZIGER, Samuel , PHAN, Gia Tung , TSIEN, Benjamin
IPC分类号： G09G5/36 , G09G5/39
摘要： Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

2. 发明申请

WO2018236798A1 POWER EFFICIENCY OPTIMIZATION IN THROUGHPUT-BASED WORKLOADS 审中-公开
公开(公告)号：WO2018236798A1
公开(公告)日：2018-12-27
申请号：PCT/US2018/038179
申请日：2018-06-19
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： PIGA, Leonardo De Paula Rosa , NAFFZIGER, Samuel , MATOSEVIC, Ivan , PAUL, Indrani
IPC分类号： G06F1/32
摘要： A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.

3. 发明公开

EP4238087A1 REFRESHING DISPLAYS USING ON-DIE CACHE 审中-实审
公开(公告)号：EP4238087A1
公开(公告)日：2023-09-06
申请号：EP21791160.1
申请日：2021-09-20
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： JAIN, Ashish , PARTAP SINGH RANA, Dhirendra , NAFFZIGER, Samuel , PHAN, Gia Tung , TSIEN, Benjamin
IPC分类号： G09G5/36 , G09G5/39

4. 发明申请

WO2023081054A1 PERFORMANCE MANAGEMENT DURING POWER SUPPLY VOLTAGE DROOP 审中-公开
公开(公告)号：WO2023081054A1
公开(公告)日：2023-05-11
申请号：PCT/US2022/048058
申请日：2022-10-27
申请人： ADVANCED MICRO DEVICES, INC.
发明人： CHAPMAN, Eric J. , KOSONOCKY, Stephen Victor , MAZUMDAR, Kaushik , KALYANASUNDHARAM, Vydhyanathan , NAFFZIGER, Samuel , SCOTT, Eric M.
IPC分类号： G06F1/324 , G06F1/3225 , G06F1/329
摘要： A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

5. 发明申请

WO2011133356A1 10T SRAM FOR GRAPHICS PROCESSING 审中-公开
标题翻译：用于图形处理的10T SRAM
公开(公告)号：WO2011133356A1
公开(公告)日：2011-10-27
申请号：PCT/US2011/032033
申请日：2011-04-12
申请人： ADVANCED MICRO DEVICES, INC. , GOLD, Spencer , KOSONOCKY, Stephen, V. , NAFFZIGER, Samuel
发明人： GOLD, Spencer , KOSONOCKY, Stephen, V. , NAFFZIGER, Samuel
IPC分类号： G11C11/412 , G11C11/413
CPC分类号： G11C11/412 , G11C11/413 , G11C15/00
摘要： A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively. The first and second pair of access parameter ports may be adapted to allow access through the first and second pair of access parameter ports if the first access parameter matches a first pre-determined value, and if the second access parameter matches a second pre-determined value.
摘要翻译：提供了一种方法，装置，计算机芯片，电路板，计算机和系统，其中数据存储在低电压，可屏蔽的存储器中。还提供了一种用数据编码的计算机可读存储设备，用于使制造设备适配以创建设备。如果与存储器单元相关联的第一访问参数与第一预定值相匹配，并且如果与存储单元相关联的第二访问参数与第二预定值匹配，则该方法包括将存储单元中的数据值存储在存储设备中。如果第一访问参数不同于第一预定值，则该方法还包括在存储设备中的存储器单元中维护数据值。该装置包括分别可操作地耦合在一起并与第一和第二访问参数相关联的第一和第二对访问参数端口。如果第一访问参数与第一预定值相匹配，则第一和第二对访问参数端口可以被适配为允许通过第一和第二对访问参数端口访问，并且如果第二访问参数与第二预定值值。

6. 发明申请

WO2020263952A1 GPU CHIPLETS USING HIGH BANDWIDTH CROSSLINKS 审中-公开
公开(公告)号：WO2020263952A1
公开(公告)日：2020-12-30
申请号：PCT/US2020/039326
申请日：2020-06-24
申请人： ADVANCED MICRO DEVICES, INC.
发明人： SALEH, Skyler J. , NAFFZIGER, Samuel , BHAGAVAT, Milind S. , AGARWAL, Rahul
IPC分类号： G06F15/78 , G06F15/173 , G06F12/0811 , G06F13/16
摘要： A chiplet system includes a central processing unit (CPU) [102] communicably coupled to a first GPU chiplet [106-1] of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus [108] and a second GPU chiplet [106-2] communicably coupled to the first GPU chiplet via a passive crosslink [118], The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

7. 发明申请

WO2019083642A1 SWIZZLING IN 3D STACKED MEMORY 审中-公开
公开(公告)号：WO2019083642A1
公开(公告)日：2019-05-02
申请号：PCT/US2018/051592
申请日：2018-09-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： WUU, John , CIRAULA, Michael K. , SCHREIBER, Russell , NAFFZIGER, Samuel
IPC分类号： G06F12/02 , G06F12/06 , G06F3/06
摘要： A processing system [100] includes a compute die [102] and a stacked memory [104] stacked with the compute die. The stacked memory includes a first memory die [104B] and a second memory die [104A] stacked on top of the first memory die. A parallel access using a single memory address is directed towards different memory banks [206, 208] of the first memory die and the second memory die. The single memory address of the parallel access is swizzled to access the first memory die and the second memory die at different physical locations.

8. 发明申请

WO2014123964A1 ADAPTIVE TEMPERATURE AND POWER CALCULATION FOR INTEGRATED CIRCUITS 审中-公开
标题翻译：集成电路的自适应温度和功率计算
公开(公告)号：WO2014123964A1
公开(公告)日：2014-08-14
申请号：PCT/US2014/014810
申请日：2014-02-05
申请人： ADVANCED MICRO DEVICES, INC. , NAFFZIGER, Samuel , LIU, Baomin
发明人： NAFFZIGER, Samuel , LIU, Baomin
IPC分类号： G05F1/565
CPC分类号： G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Methods, apparatus, and fabrication processes relating to thermal calculations of an integrated circuit device are reported. The methods may comprise determining a power consumption by a power entity of an integrated circuit, the power entity comprising at least one functional element of the integrated circuit; determining a temperature of a thermal entity, the thermal entity comprising a subset of the power entity; and adjusting at least one of a voltage or an operating frequency of at least one functional element of the power entity, based upon the temperature of the thermal entity being greater than or equal to a predetermined threshold temperature for the thermal entity.
摘要翻译：报告了与集成电路装置的热计算相关的方法，装置和制造过程。所述方法可以包括确定集成电路的功率实体的功率消耗，所述功率实体包括所述集成电路的至少一个功能元件; 确定热实体的温度，所述热实体包括所述功率实体的子集; 以及基于所述热实体的温度大于或等于所述热实体的预定阈值温度来调节所述功率实体的至少一个功能元件的电压或工作频率中的至少一个。

9. 发明申请

WO2022132463A1 MISSION MODE VMIN PREDICTION AND CALIBRATION 审中-公开
公开(公告)号：WO2022132463A1
公开(公告)日：2022-06-23
申请号：PCT/US2021/061800
申请日：2021-12-03
申请人： ADVANCED MICRO DEVICES, INC.
发明人： JAIN, Ashish , SUNDARAM, Sriram , NAFFZIGER, Samuel
IPC分类号： G06F1/3296 , G06F1/3234 , G06F1/324 , G06F1/20
摘要： The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

10. 发明公开

EP4430462A1 PERFORMANCE MANAGEMENT DURING POWER SUPPLY VOLTAGE DROOP 审中-实审
公开(公告)号：EP4430462A1
公开(公告)日：2024-09-18
申请号：EP22890633.5
申请日：2022-10-27
申请人： Advanced Micro Devices, Inc.
发明人： CHAPMAN, Eric J. , KOSONOCKY, Stephen Victor , MAZUMDAR, Kaushik , KALYANASUNDHARAM, Vydhyanathan , NAFFZIGER, Samuel , SCOTT, Eric M.
IPC分类号： G06F1/324 , G06F1/3225 , G06F1/329
CPC分类号： Y02D10/00 , G06F1/324 , G06F1/3296 , G06F1/3275 , G06F1/206 , G06F1/30 , G06F1/3206 , G06F1/28

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式