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1. 发明授权

US5805088A High speed asynchronous serial to parallel data converter 失效
标题翻译：高速异步串并转数据转换器
公开(公告)号：US5805088A
公开(公告)日：1998-09-08
申请号：US740811
申请日：1996-11-01
申请人： Adrian Stephen Butter , Leonard Ronald Chieco , James Paul Kuruts , Michael Anthony Sorna
发明人： Adrian Stephen Butter , Leonard Ronald Chieco , James Paul Kuruts , Michael Anthony Sorna
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： A device converts serial data based on one clock to parallel data based on a different, asynchronous clock. The data converter comprises one register bank including first and second registers and another register bank including third and fourth registers. A data input of the first register and a data input of the third register are coupled to receive the serial data. A data input of the second register is coupled to a data output of the first register. A data input of the fourth register is coupled to a data output of the third register. A first clock triggers the first and second registers simultaneously and a second clock triggers the third and fourth registers simultaneously. The first and second clocks alternate with each other. Fifth, sixth, seventh and eighth registers have respective data inputs coupled to respective data outputs of the first, second, third and fourth registers. A third clock triggers the fifth and sixth registers simultaneously to latch bits 0 and 2, respectively, of a series of four bits. A fourth clock triggers the seventh and eight registers simultaneously to latch bits 1 and 3, respectively, of the series of four bits.
摘要翻译：设备将基于一个时钟的串行数据转换为基于不同异步时钟的并行数据。数据转换器包括一个包括第一和第二寄存器的寄存器组和包括第三和第四寄存器的另一寄存器组。第一寄存器的数据输入和第三寄存器的数据输入被耦合以接收串行数据。第二寄存器的数据输入耦合到第一寄存器的数据输出。第四寄存器的数据输入耦合到第三寄存器的数据输出。第一时钟同时触发第一和第二寄存器，第二时钟同时触发第三和第四寄存器。第一和第二时钟彼此交替。第五，第六，第七和第八寄存器具有耦合到第一，第二，第三和第四寄存器的相应数据输出的各自的数据输入。第三个时钟同时触发第五和第六寄存器，分别锁存一系列四位的位0和2。第四个时钟同时触发第七个和第八个寄存器，分别锁存四个比特序列中的位1和3。

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