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1. 发明申请

US20090204781A1 System for Limiting the Size of a Local Storage of a Processor 失效
标题翻译：限制处理器本地存储大小的系统
公开(公告)号：US20090204781A1
公开(公告)日：2009-08-13
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00 , G06F3/00 , G06F12/02 , G06F15/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

2. 发明授权

US07533238B2 Method for limiting the size of a local storage of a processor 失效
标题翻译：用于限制处理器的本地存储器的大小的方法
公开(公告)号：US07533238B2
公开(公告)日：2009-05-12
申请号：US11208376
申请日：2005-08-19
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the 1ocal storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了一种用于限制处理器的本地存储器的大小的方法。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一个特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化上下文切换时，操作系统设置存储在本地存储限制寄存器中的值在处理器中。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

3. 发明授权

US07730279B2 System for limiting the size of a local storage of a processor 失效
标题翻译：用于限制处理器的本地存储器的大小的系统
公开(公告)号：US07730279B2
公开(公告)日：2010-06-01
申请号：US12429676
申请日：2009-04-24
申请人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
发明人： Adam P. Burns , Michael N. Day , Brian Flachs , H. Peter Hofstee , Charles R. Johns , John Liberty
IPC分类号： G06F12/00
CPC分类号： G06F12/0661 , G06F12/0223
摘要： A system for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a privileged facility and can only be accessed by the operating system running on a control processor in the multiprocessor system or the associated processor itself. The operating system sets the value stored in the local storage limit register when the operating system initializes a context switch in the processor. When the processor accesses the local storage using a request address, the local storage address corresponding to the request address is compared against the local storage limit size value in order to determine if the local storage address, or a modulo of the local storage address, is used to access the local storage.
摘要翻译：提供了用于限制处理器的本地存储器的大小的系统。与用于设置本地存储大小限制的处理器相关联地提供设施。该设施是一种特权设施，只能由在多处理器系统或相关处理器本身的控制处理器上运行的操作系统访问。当操作系统初始化处理器中的上下文切换时，操作系统设置存储在本地存储限制寄存器中的值。当处理器使用请求地址访问本地存储器时，将与请求地址相对应的本地存储地址与本地存储限制大小值进行比较，以便确定本地存储地址或本地存储地址的模数是否为用于访问本地存储。

4. 发明申请

US20120110348A1 Secure Page Tables in Multiprocessor Environments 审中-公开
标题翻译：多处理器环境中的安全页表
公开(公告)号：US20120110348A1
公开(公告)日：2012-05-03
申请号：US12917092
申请日：2010-11-01
申请人： H. Peter Hofstee , Brian Flachs , Charles R. Johns
发明人： H. Peter Hofstee , Brian Flachs , Charles R. Johns
IPC分类号： G06F12/10 , G06F12/14
CPC分类号： G06F12/1009 , G06F12/1408
摘要： A system comprises a memory module configured to store signed page table data and a selected processing element coupled to the memory module. The selected processing element is one of a plurality of processing elements, which together comprise a portion of a multiprocessor system. The selected processing element is configured to authenticate page table management code and, based on authenticated page table management code, to sign page table data that is subsequently stored in the memory module, and to verify signed page table data that is read from the memory module.
摘要翻译：系统包括被配置为存储经签名的页表数据的存储器模块和耦合到存储器模块的所选择的处理元件。所选择的处理元件是多个处理元件之一，它们一起构成多处理器系统的一部分。所选择的处理元件被配置为认证页表管理代码，并且基于经认证的页表管理代码来签名随后存储在存储器模块中的页表数据，并且验证从存储器模块读取的经签名页表数据。

5. 发明授权

US07486096B2 Method and apparatus for testing to determine minimum operating voltages in electronic devices 有权
标题翻译：用于测试以确定电子设备中的最小工作电压的方法和装置
公开(公告)号：US07486096B2
公开(公告)日：2009-02-03
申请号：US11554712
申请日：2006-10-31
申请人： Sang H. Dhong , Brian Flachs , Gilles Gervais , Charles R. Johns , Brad W. Michael , Makoto Aikawa , Iwao Takiguchi , Tetsuji Tamura
发明人： Sang H. Dhong , Brian Flachs , Gilles Gervais , Charles R. Johns , Brad W. Michael , Makoto Aikawa , Iwao Takiguchi , Tetsuji Tamura
IPC分类号： G01R31/26
CPC分类号： G01R31/3004
摘要： In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.
摘要翻译：在一个实施例中，测试系统测试被测器件（DUT）。 DUT包括一个执行内置自检（BIST程序）的内部测试控制器，内置的自检程序包括基于阵列的自动内置自检程序，离散和组合逻辑内置的自检程序，和功能体系结构验证程序（AVP），外部制造系统测试控制器管理DUT内的内部测试控制器，并确定提供DUT的电源输入电压的最小工作电压电平。逻辑模拟器提供建模能力加强DUT的最小电压电源输入运行值的开发。

6. 发明申请

US20080100328A1 Method and Apparatus for Testing to Determine Minimum Operating Voltages in Electronic Devices 有权
标题翻译：用于确定电子设备中最小工作电压的测试方法和装置
公开(公告)号：US20080100328A1
公开(公告)日：2008-05-01
申请号：US11554712
申请日：2006-10-31
申请人： Sang H. Dhong , Brian Flachs , Gilles Gervais , Charles R. Johns , Brad W. Michael , Makoto Aikawa , Iwao Takiguchi , Tetsuji Tamura
发明人： Sang H. Dhong , Brian Flachs , Gilles Gervais , Charles R. Johns , Brad W. Michael , Makoto Aikawa , Iwao Takiguchi , Tetsuji Tamura
IPC分类号： G01R31/26
CPC分类号： G01R31/3004
摘要： In one embodiment, a test system tests a device under test (DUT). The DUT includes an internal test controller that executes built-in self-test (BIST programs. Built-in self-test programs include array-based automatic built-in self-test programs, discrete and combinational logic built-in self-test programs, and functional architecture verification programs (AVPs). An external manufacturing system test controller manages the internal test controller within the DUT and determines minimum operating voltage levels for a power supply input voltage that supplies the DUT. A logic simulator provides a modeling capability to further enhance the development of minimum voltage power supply input operational values for the DUT.
摘要翻译：在一个实施例中，测试系统测试被测器件（DUT）。 DUT包括一个执行内置自检（BIST程序）的内部测试控制器，内置的自检程序包括基于阵列的自动内置自检程序，离散和组合逻辑内置的自检程序，和功能体系结构验证程序（AVP），外部制造系统测试控制器管理DUT内的内部测试控制器，并确定提供DUT的电源输入电压的最小工作电压电平。逻辑模拟器提供建模能力加强DUT的最小电压电源输入运行值的开发。

7. 发明授权

US08520740B2 Arithmetic decoding acceleration 失效
标题翻译：算术解码加速
公开(公告)号：US08520740B2
公开(公告)日：2013-08-27
申请号：US12874564
申请日：2010-09-02
申请人： Brian Flachs , Charles R. Johns , Michael A. Kutner , Brad W. Michael , Naxin Wang
发明人： Brian Flachs , Charles R. Johns , Michael A. Kutner , Brad W. Michael , Naxin Wang
IPC分类号： H04N7/12
CPC分类号： H04N19/436 , H04N19/13 , H04N19/44 , H04N19/91
摘要： Mechanisms for performing decoding of context-adaptive binary arithmetic coding (CABAC) encoded data. The mechanisms receive, in a first single instruction multiple data (SIMD) vector register of the data processing system, CABAC encoded data of a bit stream. The CABAC encoded data includes a value to be decoded and bit stream state information. The mechanisms receive, in a second SIMD vector register of the data processing system, CABAC decoder context information. The mechanisms process the value, the bit stream state information, and the CABAC decoder context information in a non-recursive manner to generate a decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms store, in a third SIMD vector register, a result vector that combines the decoded value, updated bit stream state information, and updated CABAC decoder context information. The mechanisms use the decoded value to generate a video output on the data processing system.
摘要翻译：用于执行上下文自适应二进制算术编码（CABAC）编码数据的解码的机制。这些机制在数据处理系统的第一个单指令多数据（SIMD）向量寄存器中接收位数据流的CABAC编码数据。 CABAC编码数据包括要解码的值和位流状态信息。该机制在数据处理系统的第二SIMD向量寄存器中接收CABAC解码器上下文信息。该机制以非递归方式处理值，比特流状态信息和CABAC解码器上下文信息，以生成解码值，更新的比特流状态信息和更新的CABAC解码器上下文信息。该机制在第三SIMD向量寄存器中存储组合解码值，更新位流状态信息和更新的CABAC解码器上下文信息的结果向量。这些机制使用解码的值在数据处理系统上生成视频输出。

8. 发明申请

US20120023316A1 PARALLEL LOOP MANAGEMENT 失效
标题翻译：平行环路管理
公开(公告)号：US20120023316A1
公开(公告)日：2012-01-26
申请号：US12843224
申请日：2010-07-26
申请人： Brian Flachs , Charles R. Johns , Ulrich Weigand
发明人： Brian Flachs , Charles R. Johns , Ulrich Weigand
IPC分类号： G06F9/30 , G06F9/32
CPC分类号： G06F9/3887 , G06F8/452 , G06F9/30065 , G06F9/30076 , G06F9/3806 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3853 , G06F9/3857
摘要： The illustrative embodiments comprise a method, data processing system, and computer program product having a processor unit for processing instructions with loops. A processor unit creates a first group of instructions having a first set of loops and second group of instructions having a second set of loops from the instructions. The first set of loops have a different order of parallel processing from the second set of loops. A processor unit processes the first group. The processor unit monitors terminations in the first set of loops during processing of the first group. The processor unit determines whether a number of terminations being monitored in the first set of loops is greater than a selectable number of terminations. In response to a determination that the number of terminations is greater than the selectable number of terminations, the processor unit ceases processing the first group and processes the second group.
摘要翻译：示例性实施例包括具有用于处理具有循环的指令的处理器单元的方法，数据处理系统和计算机程序产品。处理器单元创建具有第一组循环和第二组指令的第一组指令，其具有来自指令的第二组循环。第一组循环与第二组循环具有不同的并行处理顺序。处理器单元处理第一组。处理器单元在第一组处理期间监视第一组回路中的终端。处理器单元确定在第一组环路中正在监视的终端数量是否大于可选数量的终端。响应于确定终端的数量大于可选择的终端数量，处理器单元停止处理第一组并处理第二组。

9. 发明授权

US07778271B2 Method for communicating instructions and data between a processor and external devices 失效
标题翻译：在处理器和外部设备之间传送指令和数据的方法
公开(公告)号：US07778271B2
公开(公告)日：2010-08-17
申请号：US11207970
申请日：2005-08-19
申请人： Michael N. Day , Charles R. Johns , John S. Liberty , Todd E. Swanson , Thuong Q. Truong
发明人： Michael N. Day , Charles R. Johns , John S. Liberty , Todd E. Swanson , Thuong Q. Truong
IPC分类号： H04J3/00 , G06F3/00 , G06F9/00
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A method for communicating instructions and data between a processor and external devices are provided. The method makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和外部设备之间传送指令和数据的方法。该方法利用通道接口作为处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

10. 发明授权

US08024489B2 System for communicating command parameters between a processor and a memory flow controller 失效
标题翻译：用于在处理器和存储器流控制器之间传送命令参数的系统
公开(公告)号：US08024489B2
公开(公告)日：2011-09-20
申请号：US12106483
申请日：2008-04-21
申请人： Michael N. Day , Charles R. Johns , Peichun P. Liu , Todd E. Swanson , Thuong Q. Truong
发明人： Michael N. Day , Charles R. Johns , Peichun P. Liu , Todd E. Swanson , Thuong Q. Truong
IPC分类号： G06F3/00
CPC分类号： G06F13/32 , G06F13/1642
摘要： A system for communicating command parameters between a processor and a memory flow controller is provided. The system makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译：提供了一种用于在处理器和存储器流控制器之间传送命令参数的系统。该系统利用通道接口作为在处理器和存储器流控制器之间通信的主要机制。通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。这些通道可以被指定为阻塞或非阻塞。使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。因此，本发明的通道允许处理器保持在低功率状态。

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