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1. 发明申请

US20180285158A1 HYBRID LOW POWER HOMOGENOUS GRAPICS PROCESSING UNITS 审中-公开
公开(公告)号：US20180285158A1
公开(公告)日：2018-10-04
申请号：US15477026
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
发明人： Abhishek R. Appu , Altug Koker , Balaji Vembu , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Kiran C. Veernapu , Subramaniam Maiyuran , Sanjeev S. Jahagirdar , Eric J. Asperheim , Guei-Yuan Lueh , David Puffer , Wenyin Fu , Nikos Kaburlasos , Bhushan M. Borole , Josh B. Mastronarde , Linda L. Hurd , Travis T. Schluessler , Tomasz Janczak , Abhishek Venkatesh , Kai Xiao , Slawomir Grajewski
IPC分类号： G06F9/50 , G06T1/60 , G06T1/20 , G06T15/00 , G06F9/48 , G06F1/32
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

2. 发明申请

US20180285106A1 HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK 审中-公开
公开(公告)号：US20180285106A1
公开(公告)日：2018-10-04
申请号：US15477033
申请日：2017-04-01
申请人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

3. 发明授权

US10649956B2 Engine to enable high speed context switching via on-die storage 有权
公开(公告)号：US10649956B2
公开(公告)日：2020-05-12
申请号：US15477027
申请日：2017-04-01
申请人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC分类号： G06F16/13 , G06F9/38 , G06F9/30 , G06F16/11 , G06F16/172 , G06F9/46 , G06F12/1036 , G06F12/1045 , G06F12/0831
摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

4. 发明申请

US20180285374A1 ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE 审中-公开
公开(公告)号：US20180285374A1
公开(公告)日：2018-10-04
申请号：US15477027
申请日：2017-04-01
申请人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
发明人： Altug Koker , Prasoonkumar Surti , David Puffer , Subramaniam Maiyuran , Guei-Yuan Lueh , Abhishek R. Appu , Joydeep Ray , Balaji Vembu , Tomer Bar-On , Andrew T. Lauritzen , Hugues Labbe , John G. Gierach , Gabor Liktor
IPC分类号： G06F17/30 , G06F9/38 , G06F9/30
摘要： In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

5. 发明申请

US20180307487A1 GRAPHICS CONTROL FLOW MECHANISM 审中-公开
公开(公告)号：US20180307487A1
公开(公告)日：2018-10-25
申请号：US15493442
申请日：2017-04-21
申请人： Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
发明人： Subramaniam M. Maiyuran , Guei-Yuan Lueh , Supratim Pal , Gang Chen , Ananda V. Kommaraju , Joy Chandra , Altug Koker , Prasoonkumar Surti , David Puffer , Hong Bin Liao , Joydeep Ray , Abhishek R. Appu , Ankur N. Shah , Travis T. Schluessler , Jonathan Kennedy , Devan Burke
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06T1/20
摘要： An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

6. 发明申请

US20150169439A1 ISOCHRONOUS AGENT DATA PINNING IN A MULTI-LEVEL MEMORY SYSTEM 有权
标题翻译：在多级存储器系统中的异步代理数据引导
公开(公告)号：US20150169439A1
公开(公告)日：2015-06-18
申请号：US14133097
申请日：2013-12-18
申请人： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
发明人： Marc Torrant , David Puffer , Blaise Fanning , Bryan White , Joydeep Ray , Neil Schaper , Todd Witter , Altug Koker , Aditya Sreenivas
IPC分类号： G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G06F12/126
摘要： A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.
摘要翻译：处理设备包括指令执行单元，存储器代理和钉住逻辑，以在存储器请求时针对多级存储器系统中的存储器页面进行引脚。钉扎逻辑包括代理接口模块，用于从存储器代理接收指示多级存储器系统中的第一存储器页的引脚请求，所述多级存储器系统包括近存储器和远存储器。钉扎逻辑还包括存储器接口模块，用于从远端存储器检索第一存储器页面，并将第一存储器页面写入近端存储器。此外，钉扎逻辑还包括描述符表管理模块，用于将第一存储器页标记为固定在近存储器中，其中将第一存储器页标记为固定包括将对应于第一存储器页的锁存位设置在高速缓存描述符表中并且当第一存储器页面被标记为被固定时，防止第一存储器页被从近存储器逐出。

7. 发明申请

US20190303334A1 System, Apparatus And Method For Multi-Die Distributed Memory Mapped Input/Output Support 审中-公开
公开(公告)号：US20190303334A1
公开(公告)日：2019-10-03
申请号：US16447025
申请日：2019-06-20
申请人： Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
发明人： Bryan R. White , Aravindh Anantaraman , Ankur Shah , Altug Koker , David Puffer , Aditya Navale
IPC分类号： G06F13/40 , G06F13/42 , G06T1/20
摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

8. 发明申请

US20120331321A1 Processor Core with Higher Performance Burst Operation with Lower Power Dissipation Sustained Workload Mode 有权
标题翻译：处理器核心，具有更高性能突发操作，功耗更低，持续工作负载模式
公开(公告)号：US20120331321A1
公开(公告)日：2012-12-27
申请号：US13169182
申请日：2011-06-27
申请人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
发明人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
IPC分类号： G06F1/32
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G09G5/363 , G09G2330/021 , G09G2360/08 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.
摘要翻译：处理器可以在第一时间间隔的第一频率级别操作。处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。然后处理器在第二时间间隔后自动从休眠状态转换到第一频率级。因此，处理器可以以降低的功率消耗和更高的性能来操作。

9. 发明授权

US08924756B2 Processor core with higher performance burst operation with lower power dissipation sustained workload mode 有权
标题翻译：处理器内核具有更高的性能突发操作，功耗更低，持续工作负载模式
公开(公告)号：US08924756B2
公开(公告)日：2014-12-30
申请号：US13169182
申请日：2011-06-27
申请人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
发明人： Nikos Kaburlasos , Eric C. Samson , David Puffer , Lakshminarayan Jagannathan
IPC分类号： G06F1/32 , G06F1/26 , G06F1/00 , G06T1/00 , G09G5/36
CPC分类号： G06F1/324 , G06F1/3228 , G06F1/3287 , G06F1/3296 , G09G5/363 , G09G2330/021 , G09G2360/08 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： A processor may operate at a first frequency level for a first time interval. The processor automatically may transition to a sleep state from the first frequency level after the first time interval. Then the processor automatically transitions from the sleep state to the first frequency level after a second time interval. As a result the processor may operate at a reduced power consumption and higher performance.
摘要翻译：处理器可以在第一时间间隔的第一频率级别操作。处理器自动地可以在第一时间间隔之后从第一频率电平转换到睡眠状态。然后处理器在第二时间间隔后自动从休眠状态转换到第一频率级。因此，处理器可以以降低的功率消耗和更高的性能来操作。

10. 发明授权

US07120765B2 Memory transaction ordering 有权
标题翻译：内存交易排序
公开(公告)号：US07120765B2
公开(公告)日：2006-10-10
申请号：US10284596
申请日：2002-10-30
申请人： James M. Dodd , David Puffer
发明人： James M. Dodd , David Puffer
IPC分类号： G06F12/00
CPC分类号： G06F13/1626
摘要： Machine-readable media, methods, and apparatus are described which order memory transactions to increase utilization of multiple memory channels. In some embodiments, a processor may determine an issue order for memory transactions based on the memory channels that are to service the memory transactions. In some embodiments, the processor attempts to obtain an issue order that minimizes or reduces the number of idle periods experienced by the memory channels. Further, the processor may issue the memory transactions to an external memory controller for servicing in the determined issue order.
摘要翻译：描述了命令存储器事务以增加多个存储器通道的利用率的机器可读介质，方法和装置。在一些实施例中，处理器可以基于要对存储器事务进行服务的存储器通道来确定存储器事务的发布顺序。在一些实施例中，处理器尝试获得使存储器通道经历的空闲周期数量最小化或减少的问题顺序。此外，处理器可以将存储器事务发布到外部存储器控制器，以按照确定的发布顺序进行维修。

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