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1. 发明授权

US6097179A Temperature compensating compact voltage regulator for integrated circuit device 有权
标题翻译：用于集成电路器件的温度补偿紧凑型稳压器
公开(公告)号：US6097179A
公开(公告)日：2000-08-01
申请号：US264092
申请日：1999-03-08
申请人： Abhijit Ray , Raghava Madhu
发明人： Abhijit Ray , Raghava Madhu
IPC分类号： G05F3/24 , G05F3/08 , G05F1/10 , H03K17/00
CPC分类号： G05F3/245 , Y10S323/907
摘要： A voltage regulator circuit (100), coupled between a high power supply voltage (VCC) and a lower power supply voltage (VSS), provides a regulated voltage (XDD) that is greater than the high power supply voltage (VCC). The voltage regulator circuit (100) includes a temperature compensating detect circuit (102) which activates a trigger signal when the XDD voltage exceeds a predetermined level. In response to an active trigger signal, a shunt circuit (104) couples the regulated voltage (XDD) to the high power supply voltage (VCC). The regulated voltage (XDD) is translated to the detect circuit (102) by the regulated voltage (XDD) being applied to the gate of a transistor (N112) disposed between the high power supply voltage (VCC) and a detect node (108). This arrangement allows monitoring of the regulated voltage (XDD) level without loading the regulated voltage (XDD).
摘要翻译：耦合在高电源电压（VCC）和较低电源电压（VSS）之间的稳压器电路（100）提供大于高电源电压（VCC）的调节电压（XDD）。电压调节器电路（100）包括温度补偿检测电路（102），其在XDD电压超过预定电平时激活触发信号。响应于有源触发信号，分流电路（104）将调节电压（XDD）耦合到高电源电压（VCC）。调节电压（XDD）被施加到设置在高电源电压（VCC）和检测节点（108）之间的晶体管（N112）的栅极的调节电压（XDD）转换到检测电路（102）。这种布置允许监视调节电压（XDD）电平而不加载调节电压（XDD）。

2. 发明授权

US5629646A Apparatus and method for power reduction in dRAM units 失效
标题翻译： dRAM单元功率降低的装置和方法
公开(公告)号：US5629646A
公开(公告)日：1997-05-13
申请号：US407568
申请日：1995-03-21
申请人： Vinod J. Menezes , Subramani Kengeri , Raghava Madhu
发明人： Vinod J. Menezes , Subramani Kengeri , Raghava Madhu
IPC分类号： G11C11/413 , G05F3/20 , G11C11/407 , H02M3/07 , G05F1/10
CPC分类号： G05F3/205 , H02M3/07
摘要： In a DRAM unit in which the substrate bias voltage is maintained within predetermined limits by a of voltage detectors and a charge pump, a third voltage detector is provided which detects a intermediate substrate bias voltage level that is within the voltage range identified by the pair of voltage detectors. When the third voltage level detects that the intermediate substrate bias voltage has been traversed, the charge pump is activated at a reduced level to drive the substrate bias voltage to recross the intermediate substrate bias voltage level. This technique permits the DRAM unit to operate in a stand-by mode at a lower power level, especially in a standby mode of operation, than when the substrate bias voltage is maintained only by the two voltage limit detectors and a single power level charge pump.
摘要翻译：在其中通过电压检测器和电荷泵将衬底偏置电压保持在预定限度内的DRAM单元中，提供第三电压检测器，其检测在由该对电压检测器识别的电压范围内的中间衬底偏置电压电平电压检测器当第三电压电平检测到中间衬底偏置电压已经被移动时，电荷泵以降低的电平被激活，以驱动衬底偏置电压以跨越中间衬底偏置电压电平。这种技术允许DRAM单元在较低功率电平下工作，特别是在待机操作模式下，与基板偏置电压仅由两个电压限制检测器和单个功率电平电荷泵。

3. 发明授权

US5612635A High noise-margin TTL buffer circuit capable of operation with wide variation in the power supply voltage 失效
标题翻译：高噪声边缘TTL缓冲电路能够在电源电压变化很大的情况下工作
公开(公告)号：US5612635A
公开(公告)日：1997-03-18
申请号：US408514
申请日：1995-03-22
申请人： Raghava Madhu , Subramani Kengeri
发明人： Raghava Madhu , Subramani Kengeri
IPC分类号： H03K3/3565 , H03K19/0185
CPC分类号： H03K3/3565 , H03K19/018521
摘要： A buffer circuit for converting logic signals generated by apparatus implemented in a TTL technology to logic signals processed by apparatus implemented by the CMOS technology includes an input stage (10, 11, 12, 13, 17), a voltage-control (14, 15) stage for causing the buffer circuit to vary the input voltage level required to switch the state of the buffer circuit output signal, and a hysteresis stage (16) for causing the switching of the output signal level to be different for the rising and falling edges of the input signal. The voltage-control stage (14, 15) provides a improvement in the noise margin of both the VTTL(High) switching level and the VTTL(Low) switching level.
摘要翻译：用于将由TTL技术实现的装置产生的逻辑信号转换成由CMOS技术实现的装置处理的逻辑信号的缓冲电路包括输入级（10,11,12,13,17），电压控制（14,15））级，用于使缓冲电路改变切换缓冲电路输出信号的状态所需的输入电压电平，以及用于使输出信号电平的切换对于上升沿和下降沿而不同的滞后级（16）的输入信号。电压控制级（14,15）提供VTTL（高）开关电平和VTTL（低）开关电平两者的噪声容限的改进。

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