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1. 发明申请

US20100115236A1 HIERARCHICAL SHARED SEMAPHORE REGISTERS 审中-公开
标题翻译：分层分析仪
公开(公告)号：US20100115236A1
公开(公告)日：2010-05-06
申请号：US12263305
申请日：2008-10-31
申请人： Abdulla Bataineh , James Robert Kohn , Eric P. Lundberg , Timothy J. Johnson , Thomas L. Court , Gregory J. Faanes , Steven L. Scott
发明人： Abdulla Bataineh , James Robert Kohn , Eric P. Lundberg , Timothy J. Johnson , Thomas L. Court , Gregory J. Faanes , Steven L. Scott
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/30101 , G06F9/52
摘要： A multiprocessor computer system having a plurality of processing elements comprises one or more core-level hierarchical shared semaphore registers, wherein each core-level hierarchical shared semaphore register is coupled to a different processor core. Each hierarchical shared semaphore register is writable to each of a plurality of streams executing on the coupled processor core. One or more chip-level hierarchical shared semaphore registers are also coupled to plurality of processor cores, each chip-level hierarchical shared semaphore register writable to each of the plurality of processor cores.
摘要翻译：具有多个处理元件的多处理器计算机系统包括一个或多个核心级别分层共享信号量寄存器，其中每个核心级别分层共享信号量寄存器耦合到不同的处理器核心。每个分层共享信号量寄存器对于在耦合的处理器核上执行的多个流中的每一个是可写的。一个或多个芯片级别分层共享信号量寄存器也耦合到多个处理器核，每个芯片级分级共享信号量寄存器可写入多个处理器核心中的每一个。

2. 发明授权

US08601236B2 Configurable vector length computer processor 有权
标题翻译：可配置向量长度计算机处理器
公开(公告)号：US08601236B2
公开(公告)日：2013-12-03
申请号：US13409033
申请日：2012-02-29
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/00
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

3. 发明申请

US20100115234A1 CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR 审中-公开
标题翻译：可配置矢量长度计算机处理器
公开(公告)号：US20100115234A1
公开(公告)日：2010-05-06
申请号：US12263302
申请日：2008-10-31
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

4. 发明申请

US20120221830A1 CONFIGURABLE VECTOR LENGTH COMPUTER PROCESSOR 有权
标题翻译：可配置矢量长度计算机处理器
公开(公告)号：US20120221830A1
公开(公告)日：2012-08-30
申请号：US13409033
申请日：2012-02-29
申请人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
发明人： Gregory J. Faanes , Eric P. Lundberg , Abdulla Bataineh , Timothy J. Johnson , Michael Parker , James Robert Kohn , Steven L. Scott , Robert Alverson
IPC分类号： G06F15/76
CPC分类号： G06F15/8053
摘要： A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.
摘要翻译：处理器核心包括一个或多个向量单元，其可操作以在具有较短最大向量长度的细粒子矢量模式和具有较长最大向量长度的粗粒矢量模式之间进行切换。更改向量模式包括停止核心中的所有指令流执行，刷新寄存器空间中的一个或多个寄存器，重新配置寄存器空间中的一个或多个向量寄存器，以及重新启动核心中的指令执行。

5. 发明授权

US07334110B1 Decoupled scalar/vector computer architecture system and method 有权
标题翻译：去耦标量/矢量计算机架构系统及方法
公开(公告)号：US07334110B1
公开(公告)日：2008-02-19
申请号：US10643586
申请日：2003-08-18
申请人： Gregory J. Faanes , Steven L. Scott , Eric P. Lundberg , William T. Moore, Jr. , Timothy J. Johnson
发明人： Gregory J. Faanes , Steven L. Scott , Eric P. Lundberg , William T. Moore, Jr. , Timothy J. Johnson
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/30145 , G06F9/3802 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3853 , G06F9/3857 , G06F9/3861 , G06F9/3867
摘要： In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, the method comprising sending a vector instruction from the scalar processing unit to the vector dispatch unit, wherein sending includes marking the vector instruction as complete if the vector instruction is not a vector memory instruction and if the vector instruction does not require scalar operands, reading a scalar operand, wherein reading includes transferring the scalar operand from the scalar processing unit to the vector dispatch unit, predispatching the vector instruction within the vector dispatch unit if the vector instruction is scalar committed, dispatching the predispatched vector instruction if all required operands are ready, and executing the dispatched vector instruction as a function of the scalar operand.
摘要翻译：在具有标量处理单元和向量处理单元的计算机系统中，其中矢量处理单元包括矢量调度单元，将标量处理单元与矢量处理单元的操作分离的系统和方法，所述方法包括发送从标量处理单元到矢量调度单元的向量指令，其中如果向量指令不是向量存储器指令，并且如果该向量指令不需要标量操作数，读取标量操作数，则发送包括将该向量指令标记为完成，其中，读取包括将标量操作数从标量处理单元传送到向量调度单元，如果向量指令是标量提交的，则在向量调度单元内预分配向量指令，如果所有需要的操作数都准备就调度预分配向量指令，并执行调度向量指令作为标量操作数的函数。

6. 发明申请

US20100318741A1 MULTIPROCESSOR COMPUTER CACHE COHERENCE PROTOCOL 审中-公开
标题翻译：多媒体计算机缓存协议协议
公开(公告)号：US20100318741A1
公开(公告)日：2010-12-16
申请号：US12483915
申请日：2009-06-12
申请人： Steven L. Scott , Gregory J. Faanes , Abdulla Bataineh , Michael Bye , Gerald A. Schwoerer , Dennis C. Abts
发明人： Steven L. Scott , Gregory J. Faanes , Abdulla Bataineh , Michael Bye , Gerald A. Schwoerer , Dennis C. Abts
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/084
摘要： A multiprocessor computer system comprises a processing node having a plurality of processors and a local memory shared among processors in the node. An L1 data cache is local to each of the plurality of processors, and an L2 cache is local to each of the plurality of processors. An L3 cache is local the node but shared among the plurality of processors, and the L3 cache is a subset of data stored in the local memory. The L2 caches are subsets of the L3 cache, and the L1 caches are a subset of the L2 caches in the respective processors.
摘要翻译：多处理器计算机系统包括具有多个处理器的处理节点和在节点中的处理器之间共享的本地存储器。 L1数据高速缓冲存储器是多个处理器中的每一个的本地，并且L2高速缓存对于多个处理器中的每个处理器是本地的。 L3高速缓存是本地节点，但是在多个处理器之间共享，并且L3高速缓存是存储在本地存储器中的数据的子集。 L2高速缓存是L3高速缓存的子集，L1高速缓存是相应处理器中的L2高速缓存的子集。

7. 发明授权

US07519771B1 System and method for processing memory instructions using a forced order queue 有权
标题翻译：使用强制排序队列处理存储器指令的系统和方法
公开(公告)号：US07519771B1
公开(公告)日：2009-04-14
申请号：US10643577
申请日：2003-08-18
申请人： Gregory J. Faanes , Eric P. Lundberg , Steven L. Scott , Robert J. Baird
发明人： Gregory J. Faanes , Eric P. Lundberg , Steven L. Scott , Robert J. Baird
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0859
摘要： A novel system and method for processing memory instructions. One embodiment of the invention provides a method for processing a memory instruction. In this embodiment, the method includes obtaining a memory request; storing the memory request in an Initial Request Queue (IRQ); and processing the memory request from the IRQ by a cache controller, wherein processing includes: identifying a type of the memory request, and processing the memory request in both a local cache and an Force Order Queue (FOQ), wherein processing includes determining if a portion of an address associated with the memory request matches one or more partial addresses in the FOQ and, if the memory request misses in the cache and the address does not match one or more partial addresses in the FOQ, adding the memory request to the FOQ and allocating a cache line in the local cache corresponding to the local cache miss.
摘要翻译：一种用于处理存储器指令的新型系统和方法。本发明的一个实施例提供了一种用于处理存储器指令的方法。在本实施例中，该方法包括获取存储器请求; 将所述存储器请求存储在初始请求队列（IRQ）中; 以及由缓存控制器处理来自IRQ的存储器请求，其中处理包括：识别存储器请求的类型，以及在本地高速缓存和强制排队队列（FOQ）中处理存储器请求，其中处理包括确定是否与存储器请求相关联的地址的一部分匹配FOQ中的一个或多个部分地址，并且如果存储器请求在高速缓存中丢失并且该地址与FOQ中的一个或多个部分地址不匹配，则将存储器请求添加到FOQ 以及在对应于本地高速缓存未命中的本地高速缓存中分配高速缓存行。

8. 发明授权

US07082500B2 Optimized high bandwidth cache coherence mechanism 有权
标题翻译：优化高带宽缓存一致性机制
公开(公告)号：US07082500B2
公开(公告)日：2006-07-25
申请号：US10368090
申请日：2003-02-18
申请人： Steven L. Scott , Abdulla Bataineh
发明人： Steven L. Scott , Abdulla Bataineh
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/0813
摘要： A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.
摘要翻译：一种用于相干机制的方法和装置，其支持分布式存储器编程模型，其中处理器各自保持自己的存储区域，并在它们之间传送数据。支持分层编程模型，其在共享存储器节点之上使用分布式存储器语义。全局维护一致性，但缓存仅限于机器的本地区域（“节点”或“缓存域”）。目录缓存保存在片上缓存中，并且是多存储的，允许非常高的事务吞吐量。目录关联性允许目录缓存同时映射所有缓存的内容。引用关闭节点被转换为非分配引用，允许将同一访问机制（常规加载或存储）用于节点内和节点外引用。存储（Puts）到远程缓存自动更新高速缓存，而不是使缓存无效，从而允许生产者/消费者数据共享通过缓存而不是主内存发生。

9. 发明授权

US07409505B2 Optimized high bandwidth cache coherence mechanism 有权
标题翻译：优化高带宽缓存一致性机制
公开(公告)号：US07409505B2
公开(公告)日：2008-08-05
申请号：US11456781
申请日：2006-07-11
申请人： Steven L. Scott , Abdulla Bataineh
发明人： Steven L. Scott , Abdulla Bataineh
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/0813
摘要： A method and apparatus for a coherence mechanism that supports a distributed memory programming model in which processors each maintain their own memory area, and communicate data between them. A hierarchical programming model is supported, which uses distributed memory semantics on top of shared memory nodes. Coherence is maintained globally, but caching is restricted to a local region of the machine (a “node” or “caching domain”). A directory cache is held in an on-chip cache and is multi-banked, allowing very high transaction throughput. Directory associativity allows the directory cache to map contents of all caches concurrently. References off node are converted to non-allocating references, allowing the same access mechanism (a regular load or store) to be used for both for intra-node and extra-node references. Stores (Puts) to remote caches automatically update the caches instead of invalidating the caches, allowing producer/consumer data sharing to occur through cache instead of through main memory.
摘要翻译：一种用于相干机制的方法和装置，其支持分布式存储器编程模型，其中处理器各自保持自己的存储区域，并在它们之间传送数据。支持分层编程模型，其在共享存储器节点之上使用分布式存储器语义。全局维护一致性，但缓存仅限于机器的本地区域（“节点”或“缓存域”）。目录缓存保存在片上缓存中，并且是多存储的，允许非常高的事务吞吐量。目录关联性允许目录缓存同时映射所有缓存的内容。引用关闭节点被转换为非分配引用，允许将同一访问机制（常规加载或存储）用于节点内和节点外引用。存储（Puts）到远程缓存自动更新高速缓存，而不是使缓存无效，从而允许生产者/消费者数据共享通过缓存而不是主内存发生。

10. 发明授权

US08307194B1 Relaxed memory consistency model 有权
标题翻译：轻松记忆一致性模型
公开(公告)号：US08307194B1
公开(公告)日：2012-11-06
申请号：US10643754
申请日：2003-08-18
申请人： Steven L. Scott , Gregory J. Faanes , Brick Stephenson , William T. Moore, Jr. , James R. Kohn
发明人： Steven L. Scott , Gregory J. Faanes , Brick Stephenson , William T. Moore, Jr. , James R. Kohn
IPC分类号： G06F9/30
CPC分类号： G06F9/3834 , G06F9/30018 , G06F9/30036 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/34 , G06F9/3455 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/52 , G06F9/522 , G06F12/0817 , G06F12/0855 , G06F12/0862 , G06F12/1027
摘要： A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects of that relaxed memory consistency model are described. Further, a combined memory synchronization and barrier synchronization (Msync) for a multistreaming processor (MSP) system is described. Also, a global synchronization (Gsync) instruction provides synchronization even outside a single MSP system is described. Advantageously, the pipeline or queue of pending memory requests does not need to be drained before the synchronization operation, nor is it required to refrain from determining addresses for and inserting subsequent memory accesses into the pipeline.
摘要翻译：一种通过在松弛存储器一致性模型中操作的本地同步（Lsync）指令在单个流处理器（SSP）内的向量和标量运算之间和之间提供可指定排序的方法和装置。描述了该松弛记忆一致性模型的各个方面。此外，描述了用于多流处理器（MSP）系统的组合的存储器同步和屏障同步（Msync）。而且，描述了全局同步（Gsync）指令，即使在单个MSP系统外也提供同步。有利的是，在同步操作之前不需要排出未完成的存储器请求的流水线或队列，也不需要避免为后续存储器访问确定地址并将其插入流水线。

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