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    • 4. 发明授权
      US08368448B2 Delay lines, methods for delaying a signal, and delay lock loops 有权
    • Delay lines, methods for delaying a signal, and delay lock loops
    • 延迟线，延迟信号的方法和延迟锁定环
    • US08368448B2
    • 2013-02-05
    • US13426402
    • 2012-03-21
    • Tyler Gomm
    • Tyler Gomm
    • H03L7/06
    • H03L7/0818 , H03K5/133 , H03K5/14 , H03L7/0814 , H03L7/089
    • Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.
    • 公开了锁定环路，延迟线路，延迟电路和用于延迟信号的方法。 示例延迟电路包括包括多个延迟级的延迟线，每个延迟级具有输入并且还具有单个反相延迟器件，并且还包括耦合到延迟线的两相出口树，并且被配置为提供第一和 第二输出时钟信号响应于来自多个延迟级的延迟级的输入的时钟信号。 另一示例延迟电路包括被配置为提供多个延迟的时钟信号的延迟线，每个延迟的时钟信号相对于等于单个反相延迟器件的延迟的先前延迟的时钟信号具有延迟。 示例延迟电路还包括被配置为响应延迟的时钟信号提供第一和第二输出时钟信号的两相出口树。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US08073890B2 Continuous high-frequency event filter 有权
    • Continuous high-frequency event filter
    • 连续高频事件滤波器
    • US08073890B2
    • 2011-12-06
    • US11360093
    • 2006-02-22
    • Tyler Gomm , Kang Yong Kim
    • Tyler Gomm , Kang Yong Kim
    • G06F17/10
    • H03L7/0814 , G06F7/62 , G11C7/22 , G11C7/222 , H03L7/0805 , H03L7/085 , H03L7/089
    • A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.
    • 一种用于响应于由事件信号表示的N个事件来产生有效输出信号的电路和方法。 计数器电路被配置为响应于事件信号递增和递减一系列值。 耦合到计数器电路的检测逻辑被配置为检测序列的至少第一和第二值。 检测逻辑还被配置为产生有效输出信号并且响应于检测到第一值而切换到检测第二值，并且产生有效输出信号并且响应于检测到第二值而切换到检测第一值。 第一个值和第二个值用N个数值分隔。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20110254604A1 Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage 有权
    • Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage
    • 使用线路入口点控制可变延迟线来修改线路电源电压
    • US20110254604A1
    • 2011-10-20
    • US13171755
    • 2011-06-29
    • Tyler Gomm , Kang Yong Kim , Jongtae Kwak
    • Tyler Gomm , Kang Yong Kim , Jongtae Kwak
    • H03L7/06
    • H03L7/0814
    • Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.
    • 本文公开了一种VDL / DLL架构，其中至少将VDL，VccVDL的电源调节为输入信号（ClkIn）入口到VDL中的函数。 具体地说，当通过VDL的延迟相对较小（当入口点朝向VDL的右侧（或最小延迟）边缘）时，VccVDL被调节为较高，并且当延迟相对较高时（当入口点 朝向VDL的左侧（或最大延迟）边缘）。 这提供了在VDL的各个阶段的分级延迟，但是不需要分别设计每个阶段。 其他优点包括可在更宽的频率范围内操作的VDL / DLL设计，以及减少的级数，包括减少数量的缓冲级。 此外，当使用所公开的技术时，可以完全省去缓冲阶段。 另外，所公开的VDL架构可以用于可能有利的是通过作为VDL入口点的函数的可变延迟来延迟信号的任何情况。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US07872507B2 Delay lines, methods for delaying a signal, and delay lock loops 有权
    • Delay lines, methods for delaying a signal, and delay lock loops
    • 延迟线，延迟信号的方法和延迟锁定环
    • US07872507B2
    • 2011-01-18
    • US12356916
    • 2009-01-21
    • Tyler Gomm
    • Tyler Gomm
    • H03L7/06
    • H03L7/0818 , H03K5/133 , H03K5/14 , H03L7/0814 , H03L7/089
    • Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of delay stages, each of which consists of a single inverting delay device. The inputs and outputs of a selected stage are applied to a phase inverter that inverts one of the signals and applies it to a first input of a phase mixer with the same delay that the other signal is applied to a second input of the phase inverter. The delay of the signals from the selected delay element are delayed from each other by a coarse delay interval, and the phase mixer interpolates within the coarse delay interval by fine delay intervals. A phase detector compares the timing of a signal generated by the phase interpolator to the timing of a reference clock signal applied to the delay line to determine the selected delay stage and a phase interpolation value.
    • 公开了用于延迟信号的锁定环路，延迟线路和方法，例如延迟线路和使用延迟线路的延迟锁定环路包括一系列延迟级，每个延迟级由单个反相延迟器件组成。 所选择的级的输入和输出被施加到相位反相器，该相位反相器将信号中的一个反相并将其施加到相位混合器的第一输入端，并且以相同的延迟将另一信号施加到相位逆变器的第二输入端。 来自选择的延迟元件的信号的延迟相互延迟粗略的延迟间隔，并且相位混合器在粗延迟间隔内以精细的延迟间隔内插。 相位检测器将由相位插值器产生的信号的定时与施加到延迟线的参考时钟信号的定时进行比较，以确定所选择的延迟级和相位插值。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US07728639B2 Trimmable delay locked loop circuitry with improved initialization characteristics 有权
    • Trimmable delay locked loop circuitry with improved initialization characteristics
    • 具有改进初始化特性的可精确延迟锁定环路
    • US07728639B2
    • 2010-06-01
    • US12247672
    • 2008-10-08
    • Tyler Gomm , Eric Booth , Jongtae Kwak
    • Tyler Gomm , Eric Booth , Jongtae Kwak
    • H03L7/06
    • H03L7/0814
    • Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.
    • 本文公开了改进的延迟锁定环（DLL）初始化电路，其改变用于通过使用三个时钟相位来初始化可变延迟线的延迟（例如，入口点或出口点）的测量：DLL参考时钟（输入到延迟线） ，由延迟Tref修整的参考时钟，以及由延迟Tfb修剪的反馈时钟。 通过在适当的时间使用这三个相，测量意识到正（Tref）和负（Tfb）修整的Tac修整。 具体地，测量“起始”和“停止”信号每个仅通过延迟Tref和Tfb中的一个，使得测量中的误差是Tref和Tfb两者的函数。 这提高了测量的精度，使得在初始化之后不需要额外的DLL的移位，并且即使对于高时钟频率也允许宽的修整范围。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US07443216B2 Trimmable delay locked loop circuitry with improved initialization characteristics 有权
    • Trimmable delay locked loop circuitry with improved initialization characteristics
    • 具有改进初始化特性的可精确延迟锁定环路
    • US07443216B2
    • 2008-10-28
    • US11676854
    • 2007-02-20
    • Tyler Gomm , Eric Booth , Jongtae Kwak
    • Tyler Gomm , Eric Booth , Jongtae Kwak
    • H03L7/06
    • H03L7/0814
    • Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.
    • 本文公开了改进的延迟锁定环（DLL）初始化电路，其改变用于通过使用三个时钟相位来初始化可变延迟线的延迟（例如，入口点或出口点）的测量：DLL参考时钟（输入到延迟线） ，由延迟Tref修整的参考时钟，以及由延迟Tfb修剪的反馈时钟。 通过在适当的时间使用这三个相，测量意识到正（Tref）和负（Tfb）修整的Tac修整。 具体地，测量“起始”和“停止”信号每个仅通过延迟Tref和Tfb中的一个，使得测量中的误差是Tref和Tfb两者的函数。 这提高了测量的精度，使得在初始化之后不需要额外的DLL的移位，并且即使对于高时钟频率也允许宽的修整范围。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明申请
      US20080197899A1 Trimmable Delay Locked Loop Circuitry with Improved Initialization Characteristics 有权
    • Trimmable Delay Locked Loop Circuitry with Improved Initialization Characteristics
    • 具有改进的初始化特性的可精确延迟锁定回路电路
    • US20080197899A1
    • 2008-08-21
    • US11676854
    • 2007-02-20
    • Tyler Gomm , Eric Booth , Jongtae Kwak
    • Tyler Gomm , Eric Booth , Jongtae Kwak
    • H03L7/06
    • H03L7/0814
    • Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies.
    • 本文公开了改进的延迟锁定环（DLL）初始化电路，其改变用于通过使用三个时钟相位来初始化可变延迟线的延迟（例如，入口点或出口点）的测量：DLL参考时钟（输入到延迟线） ，由延迟Tref修整的参考时钟，以及由延迟Tfb修剪的反馈时钟。 通过在适当的时间使用这三个相，测量意识到正（Tref）和负（Tfb）修整的Tac修整。 具体地，测量“起始”和“停止”信号每个仅通过延迟Tref和Tfb中的一个，使得测量中的误差是Tref和Tfb两者的函数。 这提高了测量的精度，使得在初始化之后不需要额外的DLL的移位，并且即使对于高时钟频率也允许宽的修整范围。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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