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1. 发明授权

US07512739B2 Updating a node-based cache LRU tree 失效
标题翻译：更新基于节点的缓存LRU树
公开(公告)号：US07512739B2
公开(公告)日：2009-03-31
申请号：US11428581
申请日：2006-07-05
申请人： Aaron C. Sawdey , Steven P. VanderWiel
发明人： Aaron C. Sawdey , Steven P. VanderWiel
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/124 , Y10S707/99932 , Y10S707/99933 , Y10S707/99939
摘要： Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and replacing a cache line with a relatively low priority with the new cache line.
摘要翻译：示例性实施例包括用于更新Cache LRU树的方法，包括：接收新的高速缓存行; 遍历Cache LRU树，包括多个节点的Cache LRU树; 将受害者线路的选择偏向来自多条线路的具有相对较低优先级的线路; 并用新的高速缓存行替换具有较低优先级的高速缓存行。

2. 发明申请

US20080010415A1 A PSEUDO LRU TREE-BASED PRIORITY CACHE 失效
标题翻译：基于PSEUDO LRU TREE的优先级高速缓存
公开(公告)号：US20080010415A1
公开(公告)日：2008-01-10
申请号：US11428581
申请日：2006-07-05
申请人： Aaron C. Sawdey , Steven P. VanderWiel
发明人： Aaron C. Sawdey , Steven P. VanderWiel
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/124 , Y10S707/99932 , Y10S707/99933 , Y10S707/99939
摘要： Exemplary embodiments include a method for updating an Cache LRU tree including: receiving a new cache line; traversing the Cache LRU tree, the Cache LRU tree including a plurality of nodes; biasing a selection the victim line toward those lines with relatively low priorities from the plurality of lines; and replacing a cache line with a relatively low priority with the new cache line.
摘要翻译：示例性实施例包括用于更新Cache LRU树的方法，包括：接收新的高速缓存行; 遍历Cache LRU树，包括多个节点的Cache LRU树; 将受害者线路的选择偏向来自多条线路的具有相对较低优先级的线路; 并用新的高速缓存行替换具有较低优先级的高速缓存行。

3. 发明申请

US20110119322A1 On-Chip Networks for Flexible Three-Dimensional Chip Integration 有权
标题翻译：用于灵活三维芯片集成的片上网络
公开(公告)号：US20110119322A1
公开(公告)日：2011-05-19
申请号：US12617859
申请日：2009-11-13
申请人： Jian Li , Steven P. VanderWiel , Lixin Zhang
发明人： Jian Li , Steven P. VanderWiel , Lixin Zhang
IPC分类号： G06F15/16
CPC分类号： G06F15/7842
摘要： Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.
摘要翻译：提供具有多个独立和协作的片上网络的具有三维集成电路器件的互连层的机构。关于实现互连层的装置，这种装置包括包含一个或多个第一功能单元和耦合到第一集成电路层的互连层的第一集成电路层。第一集成电路层和互连层彼此集成为单个三维集成电路。互连层包括多个独立的片上通信网络，这些独立的片上通信网络是独立可操作的并且独立地能够通电和关断，每个片上通信网络包括多个点对点通信链路，多个点对点通信链路通过多个连接点。一个或多个第一功能单元耦合到互连层的第一独立片上通信网络。

4. 发明申请

US20080130667A1 DISTRIBUTED ARBITRATION MECHANISM FOR RING NETWORKS 审中-公开
标题翻译：用于环网的分布式仲裁机制
公开(公告)号：US20080130667A1
公开(公告)日：2008-06-05
申请号：US11564863
申请日：2006-11-30
申请人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
发明人： Brian M. Bass , Timothy H. Heil , Michael S. Siegel , Jeffrey R. Summers , Tiffany Tamaddoni-Jahromi , Steven P. VanderWiel
IPC分类号： H04L12/66
CPC分类号： H04L12/66
摘要： A system for employing a scalable distributed arbitration scheme, including: a plurality of stations interconnected via a ring topology for transferring data between the plurality of stations; and a bus coupling the plurality of stations in the ring topology; wherein each of the plurality of stations on the topology ring is permitted to independently make a decision when to load their data on the topology ring by evaluating a set of inputs.
摘要翻译：一种采用可扩展分布仲裁方案的系统，包括：通过环形拓扑互连的多个站，用于在多个站之间传送数据; 以及耦合所述环形拓扑中的所述多个站的总线; 其中允许拓扑环上的多个站中的每一个通过评估一组输入来独立地决定何时将其数据加载到拓扑环上。

5. 发明授权

US08386690B2 On-chip networks for flexible three-dimensional chip integration 有权
标题翻译：片上网络为灵活的三维芯片集成
公开(公告)号：US08386690B2
公开(公告)日：2013-02-26
申请号：US12617859
申请日：2009-11-13
申请人： Jian Li , Steven P. VanderWiel , Lixin Zhang
发明人： Jian Li , Steven P. VanderWiel , Lixin Zhang
IPC分类号： G06F13/00 , H01L25/00
CPC分类号： G06F15/7842
摘要： Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer.
摘要翻译：提供具有多个独立和协作的片上网络的具有三维集成电路器件的互连层的机构。关于实现互连层的装置，这种装置包括包含一个或多个第一功能单元和耦合到第一集成电路层的互连层的第一集成电路层。第一集成电路层和互连层彼此集成为单个三维集成电路。互连层包括多个独立的片上通信网络，这些独立的片上通信网络是独立可操作的并且独立地能够通电和关断，每个片上通信网络包括多个点对点通信链路，多个点对点通信链路通过多个连接点。一个或多个第一功能单元耦合到互连层的第一独立片上通信网络。

6. 发明申请

US20120038057A1 THERMAL ENHANCEMENT FOR MULTI-LAYER SEMICONDUCTOR STACKS 有权
标题翻译：多层半导体堆叠的热增强
公开(公告)号：US20120038057A1
公开(公告)日：2012-02-16
申请号：US12855854
申请日：2010-08-13
申请人： Gerald K. Bartley , Russell D. Hoover , Charles L. Johnson , Steven P. VanderWiel
发明人： Gerald K. Bartley , Russell D. Hoover , Charles L. Johnson , Steven P. VanderWiel
IPC分类号： H01L23/538 , G06F17/50 , H01L21/50
CPC分类号： H01L23/50 , G06F17/5068 , H01L23/3677 , H01L23/481 , H01L23/49838 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/0557 , H01L2224/0612 , H01L2224/06181 , H01L2224/06519 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/00014 , H01L2924/01013 , H01L2924/01033 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.
摘要翻译：一个方面的电路装置和方法利用仅在通孔之间通过在堆叠的半导体管芯的相对表面之间延伸的热，以增加多层半导体堆叠的导热性。除了通过通孔之类的数据传送之外，提供了热通孔，该通路通过电路层之间传送数据信号，并通过通孔进行通电，通孔与耦合到电路层的配电网络，使得热导率增加到可以通过堆叠中的通孔的数据携带和供电来提供。另一方面的电路装置和方法基于电流密度组织多层半导体堆叠中的电路层，以便减少堆叠中的功率分配损失。

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