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1. 发明专利

JP2002323708A THIN FILM TRANSISTOR ARRAY STRUCTURE 审中-公开
公开(公告)号：JP2002323708A
公开(公告)日：2002-11-08
申请号：JP2002026397
申请日：2002-02-04
申请人： AU OPTRONICS CORP
发明人： YU JIAN-SHEN , CHANG WEI-CHIH
IPC分类号： G02F1/1368 , G02F1/1343 , G02F1/1362 , G09F9/30 , H01L27/12 , H01L29/417 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a technology for maintaining the capacitance-coupling effect between the source electrode and the data line of a liquid crystal display device in a thin film transistor array structure. SOLUTION: By using a mask having a pattern for forming the source electrode 20c of a thin film transistor 20 and data lines 22, the source electrode 20c is formed in the peripheral region of pixels where the pixel electrode 16 is located in the vicinity of the data line 22, and the source electrode 20c and the pixel electrode 16 are coupled. Thereby the capacitance coupling effect between the pixel electrode and the data line becomes identical with the capacitance-coupling effect of the source electrode 20c and the data line 22, and the capacitance coupling effect between the source electrode 20c and the data line 22 is maintained. Therefore, even if the error of the pixel electrode occurs in the manufacturing process of the liquid crystal panel, the changes of the optical characteristics between different pixels on the panel can be avoided.

2. 发明专利

JP2006040516A Single clock driven shift register 有权
标题翻译：单时钟驱动移位寄存器
公开(公告)号：JP2006040516A
公开(公告)日：2006-02-09
申请号：JP2005212882
申请日：2005-07-22
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： TSENG JUNG-CHUN , LIU SHENG-CHAO , YU JIAN-SHEN
IPC分类号： G11C19/00 , G02F1/133 , G09G3/00 , G09G3/20 , G09G3/36 , G11C8/00 , G11C19/28
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G11C19/28
摘要： PROBLEM TO BE SOLVED: To provide a single clock driven shift register in which the overlap phenomenon of output signals is solved. SOLUTION: This shift register comprises a plurality of stage structures, wherein the M stage structure of the plurality of stage structures includes: a latch unit for latching the input signal of an M-1 stage structure based on a clock signal; a logic unit connected to the output terminal of the latch unit to apply logical operation to an output signal of the latch unit and the clock signal; and a non-overlap signal buffer connected to the output terminal of the logic unit and including at least three or more serially conncted inverters. In the non-overlap signal buffer, the output signal of the (odd-number)th inverter in a sequence coupled with the output terminal of the logic unit is fed in the latch unit of an M+1 stage structure, and the output signal of the non-overlap signal buffer of the M-1 stage structure is fed in the non-overlap signal buffer or the logic unit to delay the output signal of the non-overlap buffer. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供解决输出信号的重叠现象的单个时钟驱动移位寄存器。解决方案：该移位寄存器包括多个级结构，其中多级级结构的M级结构包括：锁存单元，用于基于时钟信号锁存M-1级结构的输入信号; 连接到所述锁存单元的输出端的逻辑单元，以对所述锁存单元的输出信号和所述时钟信号施加逻辑运算; 以及连接到逻辑单元的输出端并且包括至少三个或更多个串联连接的逆变器的非重叠信号缓冲器。在非重叠信号缓冲器中，与逻辑单元的输出端子连接的序列中的（奇数）个反相器的输出信号被馈送到M + 1级结构的锁存单元中，并且输出信号在非重叠信号缓冲器或逻辑单元中馈送M-1级结构的非重叠信号缓冲器以延迟非重叠缓冲器的输出信号。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2004350261A Sampling circuit and liquid crystal display including it 审中-公开
公开(公告)号：JP2004350261A
公开(公告)日：2004-12-09
申请号：JP2004098316
申请日：2004-03-30
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： YU JIAN-SHEN , LO WEI-JEN , CHEN CHANG-YU
IPC分类号： G02F1/1368 , G02F1/133 , G09G3/20 , G09G3/36 , H03K17/00 , H03K17/16 , H03K17/693
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/0294 , G09G2320/0219
摘要： PROBLEM TO BE SOLVED: To provide a sampling circuit which decreases a through voltage drop caused by a parasitic transistor. SOLUTION: This sampling circuit is for an analog signal and is based on a clock signal. The circuit comprises a first electrode for receiving the analog signal; a control electrode for receiving a clock signal; and a compensation device which is connected to a first thin film transistor (TFT) having a second electrode for sampling the analog signal when the clock signal is at a first logic level and to the second electrode, and decreases the feed-through voltage drop caused by parasitic capacitance between the second electrode and the control electrode of the first thin film transistor when the clock signal changes from the first logic level to a second logic level. COPYRIGHT: (C)2005,JPO&NCIPI

4. 发明专利

JP2006031019A Driving circuit and driving process of display system 审中-公开
标题翻译：显示系统的驱动电路和驱动过程
公开(公告)号：JP2006031019A
公开(公告)日：2006-02-02
申请号：JP2005207999
申请日：2005-07-19
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： CHIN KENSHI , YU JIAN-SHEN
IPC分类号： G09G3/36 , G02F1/133 , G09G3/20
CPC分类号： G09G3/2003 , G09G2300/0452 , G09G2310/0248 , G09G2310/0275 , G09G2310/0297
摘要： PROBLEM TO BE SOLVED: To provide a display system capable of operating with lower power consumption by improving a conventional display system and a method for driving the same.
SOLUTION: T display system comprises a pixel array in which a plurality of scan lines and a plurality of data lines cross each other and a plurality of pixels arrayed on a delta basis are defined, a scan driver circuit which are coupled with the scan lines and delivers a plurality of scan signals through the scan lines to select a plurality of rows of pixels, and a switching unit which is coupled with the data lines and delivers data signals through the data lines in select cycles to charge data signals in the pixels, the data lines connected to the switching unit being at least more than 3 operations of the switching units.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：通过改进传统的显示系统及其驱动方法来提供能够以更低功耗操作的显示系统。解决方案：T显示系统包括像素阵列，其中多条扫描线和多条数据线彼此交叉，并且以delta为单位排列多个像素;扫描驱动器电路，与扫描线并通过扫描线传送多条扫描信号以选择多行像素，以及切换单元，其与数据线耦合并且以选择的周期通过数据线传送数据信号，以对数据信号进行充电连接到开关单元的数据线至少是开关单元的3个操作。版权所有（C）2006，JPO＆NCIPI

5. 发明专利

JP2004046075A Method for driving display and display device 有权
标题翻译：用于驱动显示和显示设备的方法
公开(公告)号：JP2004046075A
公开(公告)日：2004-02-12
申请号：JP2003049220
申请日：2003-02-26
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： YU JIAN-SHEN
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36
CPC分类号： G09G3/3677 , G09G3/3614 , G09G3/3659 , G09G2310/065 , G09G2330/021
摘要： PROBLEM TO BE SOLVED: To provide a method for driving a display and a driver for the same.
SOLUTION: The method consists of a step of floating the gates of transistors (TRs) 121 of first and second display cells 12, a step of turning on the TRs 121 by impressing a high-voltage value to the gates of the TRs 121 of the first cells 12 and maintaining the gates of the TRs 121 of the second cells 12 at a floating state, a step of turning off the TRs 121 by impressing a low-voltage value to the gates of the TRs 121 of the first cells 12 and turning on the TRs 121 by impressing the high-voltage value to the gates of the TRs 121 of the second cells 12 and a process step of maintaining the gates of the TRs 121 of the second cells 12 at the floating state and turning off the TRs 121 by impressing the low-voltage value to the gates of the TRs 121 of the second cells 12.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种用于驱动显示器的方法和用于其的驱动器。解决方案：该方法包括使第一和第二显示单元12的晶体管（TR）121的栅极浮置的步骤，通过向TRs的栅极施加高电压值来使TRs 121接通的步骤 121，并且将第二单元12的TR 121的栅极保持在浮置状态，通过向第一单元的TR 121的栅极施加低电压值来关闭TR 121，并且通过将高电压值施加到第二单元12的TR 121的栅极并且将第二单元12的TR 121的栅极保持在浮置状态并关闭的处理步骤，接通TR 121 通过将低电压值施加到第二电池单元12的TRs 121的门，TRs 121。版权所有（C）2004，JPO

6. 发明专利

JP2004015797A Level shift circuit 有权
公开(公告)号：JP2004015797A
公开(公告)日：2004-01-15
申请号：JP2002360360
申请日：2002-12-12
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： YU JIAN-SHEN
IPC分类号： H03K19/0175 , H03K3/356
CPC分类号： H03K3/356147
摘要： PROBLEM TO BE SOLVED: To provide a level shift circuit which is appropriate for low temperature polysilicon (LTPS). SOLUTION: A gate of a PMOS transistor is connected to an input terminal, and a source of a PMOSS transistor is connected to a power source. A drain of an NMOS transistor is connected to a drain of the PMOS transistor. A source of the NMOS transistor is connected to a reverse input terminal. A gate of the NMOS transistor is connected to the power source. In a reverse logic gate, its first terminal is connected to the drain of the NMOS transistor, and its second terminal is connected to an output terminal. COPYRIGHT: (C)2004,JPO

7. 发明专利

JP2007184076A Shift register 有权
标题翻译：移位寄存器
公开(公告)号：JP2007184076A
公开(公告)日：2007-07-19
申请号：JP2006325407
申请日：2006-12-01
申请人： Au Optronics Corp , 友達光電股▲ふん▼有限公司
发明人： YU JIAN-SHEN
IPC分类号： G11C19/28 , G09G3/20 , G09G3/36 , G11C19/00
CPC分类号： G11C19/28
摘要： PROBLEM TO BE SOLVED: To provide a shift register which turns off each stage without making wiring between stages complicated. SOLUTION: Each stage SA of the shift register is provided with an enable circuit 1 and a disenable circuit 2. The disenable circuit 2 turns off the enable circuit 1 by the supply of a high voltage to the disable circuit 2 from the outside of the shift register in a period except a period in which a control signal is inputted to the enable circuit 1 and the next control signal is outputted from the enable circuit 1. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种移位寄存器，该移位寄存器在不使级之间的布线复杂的情况下关闭每个级。
解决方案：移位寄存器的每个级SA都设置有使能电路1和不可用电路2.不可用电路2通过从外部向禁用电路2提供高电压来关断使能电路1 除了将控制信号输入到使能电路1的时段之外的期间内的移位寄存器中，并且从使能电路1输出下一个控制信号。（C）2007，JPO＆INPIT

8. 发明专利

JP2005129211A Controller for bidirectional shift register, and bidirectional shift register circuit 有权
标题翻译：双向移位寄存器控制器和双向移位寄存器电路
公开(公告)号：JP2005129211A
公开(公告)日：2005-05-19
申请号：JP2004293750
申请日：2004-10-06
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： YU JIAN-SHEN
IPC分类号： G09G3/20 , G09G3/36 , G11C19/00 , G11C19/28 , H03K19/20 , H03K21/00
CPC分类号： G11C19/00 , G11C19/28
摘要： PROBLEM TO BE SOLVED: To provide a shift register control circuit for completely turning off the transistor of the control circuit. SOLUTION: The bidirectional shift register circuit includes a plurality of shift resisters, input and output terminals, and a plurality of bidirectional shift control elements to cope with each shift register. The circuit includes a first input terminal connected to the output terminal of a first register, and a second input terminal connected to the output terminal of a second shift register. The controller provides first and second control voltages, and the first and second voltages have different levels. A combination circuit provides an instruction signal, based on the first and second control signals and guides an input signal, provided from the first or second shift register toward the input terminal of a corresponding shift register. This combination circuit comprises NOR gates or NAND gates. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于完全关闭控制电路的晶体管的移位寄存器控制电路。解决方案：双向移位寄存器电路包括多个移位寄存器，输入和输出端子以及多个双向移位控制元件以对应每个移位寄存器。电路包括连接到第一寄存器的输出端的第一输入端和连接到第二移位寄存器的输出端的第二输入端。控制器提供第一和第二控制电压，并且第一和第二电压具有不同的电平。组合电路基于第一和第二控制信号提供指令信号，并将从第一或第二移位寄存器提供的输入信号引导到相应移位寄存器的输入端。该组合电路包括NOR门或NAND门。版权所有（C）2005，JPO＆NCIPI

9. 发明专利

JP2004362745A Shift register capable of changing over output sequence of signal 审中-公开
公开(公告)号：JP2004362745A
公开(公告)日：2004-12-24
申请号：JP2004105496
申请日：2004-03-31
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： YU JIAN-SHEN , LU SHI-HSIANG , KUO CHUNG-HONG
IPC分类号： G02F1/133 , G09G3/20 , G09G3/36 , G11C19/00 , G11C19/28
CPC分类号： G11C19/28 , G11C19/00
摘要： PROBLEM TO BE SOLVED: To provide a bidirectional shift-register circuit which can be normally operated under a clock signal of a low voltage. SOLUTION: The bidirectional shift-register circuit is capable of changing over at least the clock signal of the low voltage, a first direction signal and a second direction signal, and a signal for outputting clock data by the different sequences of scanning. The shift-resister circuit includes a plurality of shift-register units, a bidirectional scanning control circuit and a voltage level shifter connected to the individually corresponding shift-register units. Each shift-register unit includes input terminals, output terminals and clock input terminals which receive and connect the low voltages of the clock signals. COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2004348940A Shift register circuit 审中-公开
公开(公告)号：JP2004348940A
公开(公告)日：2004-12-09
申请号：JP2004106108
申请日：2004-03-31
申请人： Au Optronics Corp , 友達光電股▼ふん▲有限公司
发明人： YU JIAN-SHEN
IPC分类号： G11C19/00 , G09G3/20 , G09G3/36 , G11C19/18 , G11C19/28
CPC分类号： G11C19/184 , G11C19/28
摘要： PROBLEM TO BE SOLVED: To provide a shift register circuit for reducing the number of internal capacitors of a transistor connected to a clock signal. SOLUTION: In this shift register circuit which has a plurality of shift register units connected in series and transmits the clock signal, an inverted clock signal and first voltage, each of the shift register units includes a first transistor having a gate and a first source/drain, a converter, a second transistor having a second source/drain, a third transistor having a second source/drain, and a fourth transistor having a second source/drain to be connected to first voltage. COPYRIGHT: (C)2005,JPO&NCIPI

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