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    • 3. 发明专利
    • Improvements relating to transistor circuits
    • GB1095041A
    • 1967-12-13
    • GB165264
    • 1964-01-14
    • ASS ELECT IND
    • DREW ANTHONY JOHNGORSKI-POPIEL JERZY
    • H03F3/343
    • 1,095,041. Transistor circuits. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Dec. 17, 1964 [Jan. 14, 1964], No. 1652/64. Heading H3T. A circuit having selectable current gain characteristics comprises a first transistor T1 having impedances R1, R2 connected as shown, impedance R1 being connected in series with an electrode of a further transistor T2 in such a way that the overall current gain of the circuit is dependent on the ratio of the moduli of R1 and R2. As shown in Fig. 11, terminal B of unit U (Fig. 1) is connected to the collector of T2 whilst the collector of T1 is connected to the base of T2. In Fig. 3 (not shown) terminals B or E are connected to the base of T2. In Figs. 4 to 9 (not shown) terminals E or B of unit U are connected to the emitter of T2. In Figs. 10 to 15 (not shown) terminals B or E of unit U are connected to the collector of T2. In all embodiments, the collector of T1 is either connected to ground through an negligible impedance or connected to one of the remaining electrodes of T2. In Fig. 11, base bias for T1 may be provided by a Zener diode connected in series with terminal B. In Fig. 2 (not shown) T1 is replaced by a compound emitter follower. Impedances R1, R2 should be high compared with the emitter and base resistances of T1; this may result in an increase of input impedance. Expressions are given for commonbase and common-emitter current gain for all embodiments.
    • 9. 发明专利
    • Improvements relating to negative impedance converter circuits
    • GB1048093A
    • 1966-11-09
    • GB489064
    • 1964-02-05
    • ASS ELECT IND
    • DREW ANTHONY JOHNGORSKI-POPIEL JERZY
    • H03K3/281H04B3/18
    • 1,048,093. Negative impedance converters. ASSOCIATED ELECTRICAL INDUSTRIES Ltd. Feb. 2, 1965 [Feb. 5, 1964], No. 4890/64. Heading H3T. To correct for parasitic impedances and offset voltagers or currents in a negative impedance converter, the two-port converter circuit of the invention is provided with one or more of (a) a source of D.C. potential connected to a terminal of the second port to render the potentials at each terminal the same, (b) a correcting element, of similar value to the series parasitic impedance and/or offset voltage appearing at the first port, which is connected in series with the second port, ((c) a correcting element, of similar value to the shunt parasitic impedance and/or associated offset current appearing at the second port, which is connected in parallel with the first port. In the circuit of Fig. 7 the correcting impedance is resistor R 11 and resistor R 5 in the collector circuit of transistor T 1 serves as an extra D.C. source to correct the offset current appearing at the second source. At the second port the series correcting impedance is resistor R 7 and the output port terminal potentials are rendered equal by Zener diode ZD. The conversion ratio of the circuit, preferably - 1, is determined by the ratio of R 1 to R 2 and may be altered by the resistors R 8 , R 9 , R 10 acting to alter the effective impedance of R 2 . R 9 is altered to maintain the potential charge across R 8 equal to zero. A simplified version of the circuit of Fig. 7 is illustrated in Fig. 8 (not shown). In Fig. 9 (not shown) the resistors R 3 , R 4 of Fig. 7 are replaced by transistors T 3 , T 4 and the current and voltage correcting elements comprise transistors T 5 , T 6 . The single transistors of the circuits may be replaced by Darlington compound transistors (Fig. 10, not shown). A further alternative (Fig. 13, not shown) is a circuit based on a bridge arrangement (Fig. 11. not shown).