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1. 发明专利

JP2003282844A PLASMA ETCHING OF Ir AND PZT USING HARD MASK AND Cl2/N2/O2 AND Cl2/CHF3/O2 CHEMISTRY. 审中-公开
标题翻译：使用硬掩模和Cl2 / N2 / O2和Cl2 / CHF3 / O2化学的Ir和PZT的等离子体蚀刻。
公开(公告)号：JP2003282844A
公开(公告)日：2003-10-03
申请号：JP2003066300
申请日：2003-03-12
申请人： Agilent Technol Inc , Applied Materials Inc , Texas Instruments Inc , アジレント・テクノロジーズ・インク , アプライドマテリアルズインコーポレイテッド , テキサスインスツルメンツインコーポレイテッド
发明人： YING CHENTSAU , SAKODA TOMOYUKI , CHI CHIU
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L21/8246 , H01L27/105
CPC分类号： H01L21/32139 , H01L21/31122 , H01L21/32136 , H01L28/55
摘要： PROBLEM TO BE SOLVED: To provide a precise and efficient etching process to fabricate a FeRAM cell with high memory densities and high throughput.
SOLUTION: Processes for etching PZT and/or forming a ferroelectric capacitor with Ir/IrOx electrodes (350/355, 300/335) and PZT ferroelectric layer (340) use a titanium-containing hard mask (360), a chlorine/oxygen-based plasma, and a hot substrate, typically at about 350°C. The processes add a fluorine- containing compound such as CHF
3 to the chlorine/oxygen-based plasma for etching of the PZT layer and add nitrogen to improve sidewall profiles when etching Ir layers (350/330). The chlorine/oxygen-based plasmas provide good selectivity with high etch rates for Ir and PZT layers and low etch rates for the hard mask.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供精确和有效的蚀刻工艺来制造具有高存储密度和高生产量的FeRAM单元。解决方案：用Ir / IrOx电极（350/355,3300/335）和PZT铁电层（340）蚀刻PZT和/或形成铁电电容器的工艺使用含钛硬掩模（360），氯 /氧基等离子体和热衬底，通常在约350℃。该方法将氯基/氧基等离子体中的含氟化合物如CHF 3添加到PZT层中，并在蚀刻Ir层（350/330）时添加氮气以改善侧壁轮廓。氯/氧基等离子体提供良好的选择性，对于Ir和PZT层具有高蚀刻速率，并且硬掩模具有低蚀刻速率。版权所有（C）2004，JPO

2. 发明专利

JP2004349687A Method of fabricating magnetoresistive random access memory (mram) device 审中-公开
标题翻译：制造磁阻随机存取存储器（MRAM）器件的方法
公开(公告)号：JP2004349687A
公开(公告)日：2004-12-09
申请号：JP2004123262
申请日：2004-04-19
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： YING CHENTSAU , CHEN XIAOYI , YAN CHUN , KUMAR AJAY
IPC分类号： H01L21/3065 , C23F4/00 , H01F41/30 , H01L21/02 , H01L21/3213 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L43/10 , H01L43/12
CPC分类号： H01L21/02071 , B82Y25/00 , B82Y40/00 , C23F4/00 , H01F41/308 , H01L21/32136 , H01L43/12
摘要： PROBLEM TO BE SOLVED: To provide an improved method for etching magnetic materials for manufacturing a magnetoresistive random access memory (MRAM) device.
SOLUTION: Respective layers of a multi-layer magnetic stack with are etched, using process sequence including plasma-etching steps 108, 112, 116 and plasma-treatment steps 110, 114, 118, followed by those. The plasma-treatment steps 110, 114, 118 use plasma comprising an inert gas to remove the residues formed during the plasma-etching steps 108, 112, 116.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于蚀刻用于制造磁阻随机存取存储器（MRAM）装置的磁性材料的改进方法。解决方案：使用包括等离子体蚀刻步骤108,112,116和等离子体处理步骤110,114,118的处理顺序蚀刻多层磁性堆叠的各层，其次是那些。等离子体处理步骤110,114,118使用包含惰性气体的等离子体处理步骤108,112,116中形成的残留物。（C）2005，JPO＆NCIPI

3. 发明专利

SG11202000967VA MICROWAVE REACTOR FOR DEPOSITION OR TREATMENT OF CARBON COMPOUNDS 未知
公开(公告)号：SG11202000967VA
公开(公告)日：2020-02-27
申请号：SG11202000967V
申请日：2018-08-08
申请人： APPLIED MATERIALS INC
发明人： LIANG QIWEI , ZHOU JIE , KHAN ADIB M , PISHARODY GAUTAM , CHEN GUANNAN , YING CHENTSAU , NEMANI SRINIVAS D
IPC分类号： H01J37/32
摘要： A plasma reactor for processing a workpiece includes a chamber having a dielectric window, a workpiece support to hold a workpiece in the chamber, a rotary coupling comprising a stationary stage configured to be coupled to a microwave source and a rotatable stage having an axis of rotation, a microwave antenna and overlying the dielectric window of the chamber, a rotary actuator to rotate the microwave antenna, and a process gas distributor including a gas distribution ring surrounding the workpiece support. The microwave antenna includes at least one conduit coupled to the rotary stage. The gas distribution ring including a cylindrical chamber liner separating a circular conduit from the chamber and a plurality of apertures extending radially through the liner to connect the conduit to the chamber.

4. 发明专利

SG11201912265WA METHODS OF FORMING A STACK OF MULTIPLE DEPOSITED SEMICONDUCTOR LAYERS 未知
公开(公告)号：SG11201912265WA
公开(公告)日：2020-01-30
申请号：SG11201912265W
申请日：2018-07-03
申请人： APPLIED MATERIALS INC
发明人： MIAO LIYAN , YING CHENTSAU , HAN XINHAI , LIN LONG
IPC分类号： H01L21/02
摘要： Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.

5. 发明申请

WO0049651A9 IMPROVED MASKING METHODS AND ETCHING SEQUENCES FOR PATTERNING ELECTRODES OF HIGH DENSITY RAM CAPACITORS 审中-公开
标题翻译：改进高密度RAM电容器电极的掩蔽方法和蚀刻顺序
公开(公告)号：WO0049651A9
公开(公告)日：2002-05-02
申请号：PCT/US0004240
申请日：2000-02-17
申请人： APPLIED MATERIALS INC
发明人： HWANG JENG H , MAK STEVE S Y , LIN TRUE-LON , YING CHENTSAU
IPC分类号： H01L21/302 , C23F4/00 , H01L21/02 , H01L21/3065 , H01L21/3213 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/60 , C23F4/00 , H01L21/32136 , H01L21/32139
摘要： A method of etching a noble metal electrode layer disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.35 mu m and having a noble metal profile equal to or greater than about 80 DEG . The method comprises heating the substrate to a temperature greater than about 150 DEG C, and etching the noble metal electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising a gas selected from the group consisting of nitrogen, oxygen, a halogen (e.g., chlorine), argon, and a gas selected from the group consisting of BCl3, HRBr, and SiCl4 mixtures thereof. A semiconductor device having a substrate and a plurality of noble metal electrodes supported by the substrate. The noble metal electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 mu m and a platinum profile equal to or greater than about 85 DEG . Masking methods and etching sequences for patterning high density RAM capacitors are also provided. The substrate may be heated by a pedestal in a reactor chamber having a dielectric window including a deposit-receiving surface having a surface finish comprising a peak-to-valley roughness height with an average height value of greater than about 1,000 ANGSTROM .
摘要翻译：一种蚀刻设置在基板上的贵金属电极层的方法，以制造半导体器件，该半导体器件包括间隔等于或小于约0.35μm并具有等于或大于约80°的贵金属形状的多个电极。该方法包括将衬底加热至大于约150℃的温度，并通过采用包含选自氮，氧，卤素的气体的蚀刻剂气体的高密度电感耦合等离子体来蚀刻贵金属电极层（例如氯），氩气和选自BCl 3，HRBr和SiCl 4混合物的气体。一种半导体器件，具有基板和由基板支撑的多个贵金属电极。贵金属电极具有包括等于或小于约0.3μm的值和等于或大于约85°的铂分布的尺寸（例如，宽度）。还提供了用于图案化高密度RAM电容器的掩模方法和蚀刻顺序。衬底可以由具有介电窗口的反应室中的基座加热，所述电介质窗口包括具有表面光洁度的沉积物接收表面，所述沉积物接收表面包括具有平均高度值大于约1,000安培的峰 - 谷粗糙度高度。

6. 发明申请

WO0182344A3 METHOD OF PATTERNING LEAD ZIRCONIUM TITANATE AND BARIUM STRONTIUM TITANATE 审中-公开
标题翻译：铅钛酸锶和钛酸锶钡的方法
公开(公告)号：WO0182344A3
公开(公告)日：2002-02-28
申请号：PCT/US0112905
申请日：2001-04-20
申请人： APPLIED MATERIALS INC
发明人： YING CHENTSAU , HWANG JENG H , YAMAUCHI HIDEYUKI , PARK SEAYOUL , KAWASE YOHEI
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/316
CPC分类号： H01L21/31122 , H01L21/31691
摘要： In an embodiment of the present invention, a method is provided of patterning PZT layers or BST layers. For example, a PZT layer or a BST layer is plasma etched through a high-temperature-compatible mask such as a titanium nitride (TiN) mask, using a plasma feed gas comprising as a primary etchant boron trichloride (BCl3) or silicon tetrachloride (SiCl4). Although BCl3 or SiCl4 may be used alone as the etchant plasma source gas, it is typically used in combination with an essentially inert gas. Preferably the essentially inert gas is argon. Other potential essentially inert gases which may be used include xenon, krypton, and helium. In some instances O2 or N2, or Cl2, or a combination thereof may be added to the primary etchant to increase the etch rate of PZT or BST relative to adjacent materials, such as the high-temperature-compatible masking material. A TiN masking material can easily be removed without damaging underlying oxides. The selectivity of PZT or BST relative to TiN is very good, with the ratio of the etch rate of the PZT film to the etch rate of the TiN mask typically being better than 20:1. In addition, the etch rate for PZT using a BCl3 - comprising plasma source gas is typically in excess of 2,000 ANGSTROM per minute. A substrate bias power is applied to direct ions produced from the BCl3 or SiCl4 toward the surface to be etched. The bias power is controlled to avoid sputtering of a conductive layer or layers in contact with the PZT layer, so that the surface of the etched PZT is not contaminated by a conductive material, which can cause the semiconductor device which includes the patterned PZT to short out.
摘要翻译：在本发明的一个实施例中，提供了一种图案化PZT层或BST层的方法。例如，使用包含作为主要蚀刻剂三氯化硼（BCl 3）或四氯化硅（BCl 3）的等离子体进料气体，通过诸如氮化钛（TiN）掩模的高温兼容掩模等离子体蚀刻PZT层或BST层四氯化硅）。尽管BCl 3或SiCl 4可以单独用作蚀刻剂等离子体源气体，但通常与基本上惰性气体组合使用。优选地，基本上惰性的气体是氩气。可以使用的其它潜在的基本上惰性的气体包括氙，氪和氦。在一些情况下，可以向初级蚀刻剂中加入O 2或N 2或Cl 2或其组合以增加PZT或BST相对于相邻材料（例如高温兼容掩蔽材料）的蚀刻速率。可以容易地去除TiN掩模材料而不损坏潜在的氧化物。 PZT或BST相对于TiN的选择性非常好，PZT膜的蚀刻速率与TiN掩模的蚀刻速率之比通常优于20：1。此外，使用包含等离子体源气体的BCl 3的PZT的蚀刻速率通常超过每分钟2,000安培。施加衬底偏置功率以将从BCl 3或SiCl 4产生的离子导向待蚀刻的表面。控制偏置功率以避免溅射与PZT层接触的导电层，使得蚀刻的PZT的表面不被导电材料污染，这可导致包括图案化PZT的半导体器件短路出。

7. 发明申请

WO0049650A9 IRIDIUM ETCHING METHODS FOR ANISOTROPHIC PROFILE 审中-公开
标题翻译：红斑蚀刻方法用于各向异性剖面
公开(公告)号：WO0049650A9
公开(公告)日：2001-09-20
申请号：PCT/US0004058
申请日：2000-02-16
申请人： APPLIED MATERIALS INC
发明人： HWANG JENG H , YING CHENTSAU , JIN GUANGXIANG , MAK STEVE S Y
IPC分类号： C23F4/00 , H01L21/02 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/8246 , H01L27/105
CPC分类号： H01L28/60 , C23F4/00 , H01L21/32136 , H01L21/32139
摘要： A method of etching an electrode layer (e.g., a platinum electrode layer or an iridium electrode layer) disposed on a substrate to produce a semiconductor device including a plurality of electrodes separated by a distance equal to or less than about 0.3 mu m and having a profile equal to or greater than about 85 DEG . The method comprises heating the substrate to a temperature greater than about 150 DEG C, and etching the electrode layer by employing a high density inductively coupled plasma of an etchant gas comprising oxygen and/or chlorine, argon and a gas selected from the group consisting of BC13, HBr, HC1 and mixtures thereof. A semiconductor device having a substrate and a plurality of electrodes supported by the substrate. The electrodes have a dimension (e.g., a width) which include a value equal to or less than about 0.3 mu m and a profile equal to or greater than about 85 DEG .
摘要翻译：一种蚀刻设置在基板上的电极层（例如，铂电极层或铱电极层）的方法，以制造半导体器件，该半导体器件包括间隔等于或小于约0.3μm的多个电极，并具有概况等于或大于约85°。该方法包括将衬底加热到大于约150℃的温度，并且通过采用包含氧和/或氯，氩和选自以下的气体的气体的高密度电感耦合等离子体来蚀刻电极层： BC13，HBr，HC1及其混合物。一种半导体器件，具有基板和由基板支撑的多个电极。电极具有包括等于或小于约0.3μm的值和等于或大于约85°的轮廓的尺寸（例如，宽度）。

8. 发明申请

WO0049202A2 IMPROVED ETCHING METHODS FOR ANISOTROPIC PLATINUM PROFILE 审中-公开
标题翻译：改进各向异性铂形貌的蚀刻方法
公开(公告)号：WO0049202A2
公开(公告)日：2000-08-24
申请号：PCT/US0004015
申请日：2000-02-16
申请人： APPLIED MATERIALS INC
发明人： HWANG JENG H , YING CHENTSAU , CHIANG KANG-LIE , MAK STEVE S Y
IPC分类号： H01L21/28 , C23F4/00 , H01L21/02 , H01L21/302 , H01L21/3065 , H01L21/3213 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , C23F
CPC分类号： H01L28/60 , C23F4/00 , H01L21/32136 , H01L21/32139
摘要： A method for etching a platinum electrode layer disposed on a substrate to produce a semiconductor device including a plurality of platinum electrodes. The method comprises heating the substrate to a temperature greater than about 150 DEG C, and etching the platinum electrode layer by employing a plasma of an etchant gas comprising nitrogen and a halogen (e.g. chlorine), and a gas selected from the group consisting of a noble gas (e.g. argon), BCl3, HBr, SiCl4 and mixtures thereof. The substrate may be heated in a reactor chamber having a dielectric window including a deposit-receiving surface having a surface finish comprising a peak-to-valley roughness height with an average height value of greater than about 1000 ANGSTROM .
摘要翻译：一种蚀刻设置在基板上的铂电极层的方法，以制造包括多个铂电极的半导体器件。该方法包括将衬底加热到大于约150℃的温度，并且通过采用包含氮和卤素（例如氯）的蚀刻剂气体的等离子体蚀刻铂电极层，以及选自以下的气体：惰性气体（例如氩），BCl 3，HBr，SiCl 4及其混合物。可以在具有电介质窗口的反应室中加热衬底，该电介质窗口包括具有表面光洁度的沉积物接收表面，该表面光洁度包括平均高度值大于约1000埃的峰谷表面粗糙度高度。

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