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1. 发明专利

DE3789142T2 未知
公开(公告)号：DE3789142T2
公开(公告)日：1994-05-26
申请号：DE3789142
申请日：1987-12-18
申请人： APPLIED MATERIALS INC
发明人： WANG DAVID NIN-KOU , WHITE JOHN M , LAW KAM S , LEUNG CISSY , UMOTOY SALVADOR P , COLLINS KENNETH S , ADAMIK JOHN A , PERLOV ILYA , MAYDAN DAN
IPC分类号： C23C16/48 , C23C16/04 , C23C16/40 , C23C16/42 , C23C16/44 , C23C16/455 , C23C16/46 , C23C16/50 , C23C16/509 , C23C16/54 , C23F4/00 , C30B25/14 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/683
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor (10) is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor (16) and wafer fingers (20) which collectively remove the wafer (15) from a robot transfer blade (24) and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold (26) then return the wafer to the blade. A combined RF/gas feed-through device (36) protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold (26) is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust fases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressure including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone on in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

2. 发明专利

JP2002060945A DEPOSITION OF TEOS OXIDE USING PULSE RF PLASMA 失效
公开(公告)号：JP2002060945A
公开(公告)日：2002-02-28
申请号：JP2001109076
申请日：2001-04-06
申请人： APPLIED MATERIALS INC
发明人： GOTO HARUHIRO H , TAKEHARA TAKAKO , CARL A SORENSEN , WILLIAM R HIRSCHBERGER , LAW KAM S
IPC分类号： C23C16/40 , C03C17/245 , H01L21/31 , H05H1/24
摘要： PROBLEM TO BE SOLVED: To provide a method for depositing a silicon dioxide film of high quality on a substrate by using a plasma enhanced chemical vapor phase growth and TEOS(Tetra Ethyl Ortho Silicate). SOLUTION: This method includes a step in which a high frequency pulse power source used for generating TEOS oxide plasma is fed to control the deposition rate of silicon dioxide on a substrate. The obtained silicon dioxide film shows good electrical and mechanical film characteristics in the application of forming a thin film transistor.

3. 发明专利

JP2004165682A Multi-step cvd method for thin film transistor 有权
标题翻译：薄膜晶体管的多步CVD方法
公开(公告)号：JP2004165682A
公开(公告)日：2004-06-10
申请号：JP2003413631
申请日：2003-12-11
申请人： Applied Materials Inc , アプライドマテリアルズインコーポレイテッドApplied Materials,Incorporated
发明人： LAW KAM S , ROBERTSON ROBERT , KOLLRACK MICHAEL , LEE ANGELA T , TAKEHARA TAKAKO , FENG GUOFU J , MAYDAN DAN
IPC分类号： H01L21/205 , C23C16/24 , C23C16/34 , H01L21/31 , H01L21/318 , H01L21/336 , H01L29/786
CPC分类号： H01L29/66765 , C23C16/24 , C23C16/345
摘要： PROBLEM TO BE SOLVED: To provide a method for depositing a silicon nitride layer and an amorphous silicon layer on a thin film transistor substrate in a sufficient rate of deposition and for maintaining a high level quality of the film.
SOLUTION: On the top surface of a g-SiN
x film 72 of average quality deposited at a high rate of deposition, a high-quality g-SiN
x film 74 is deposited at a low rate of deposition, and after that the amorphous silicon layer is deposited. An interface 76 is formed after a high-quality a-Si layer 78 is deposited at a low rate of deposition on the g-SiN
x film 74, and then an average quality a-Si layer 80 is deposited, which completes the arrangement of the a-Si layers. If the interface is with the active semiconductor layer of amorphous silicon, the process can be applied to other purposes. This is applicable to a BCETFT (back channel etch thin film transistor) device and an ESTFT (etch stop thin film transistor) device as well.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种在薄膜晶体管基板上以足够的沉积速率沉积氮化硅层和非晶硅层并保持膜的高质量的方法。解决方案：在以高沉积速率沉积的平均质量的g-SiN x SB薄膜72的顶表面上，高质量的g-SiN x 以低沉积速率沉积膜74，然后沉积非晶硅层。在高质量的a-Si层78以低沉积速率沉积在g-SiN x SB薄膜74上之后形成界面76，然后平均质量a-Si层80为沉积，其完成了a-Si层的排列。如果界面与非晶硅的有源半导体层一起使用，则该过程可以应用于其它目的。这也适用于BCETFT（背沟道蚀刻薄膜晶体管）器件和ESTFT（蚀刻停止薄膜晶体管）器件。版权所有（C）2004，JPO

4. 发明专利

JP2000012870A MULTISTAGE CVD METHOD FOR THIN-FILM TRANSISTOR 失效
公开(公告)号：JP2000012870A
公开(公告)日：2000-01-14
申请号：JP9782199
申请日：1999-04-05
申请人： APPLIED MATERIALS INC
发明人： LAW KAM S , ROBERTSON ROBERT , KOLLRACK MICHAEL , LEE ANGELA T , TAKEHARA TAKAKO , FENG GUOFU J , MAYDAN DAN
IPC分类号： H01L21/205 , C23C16/24 , C23C16/34 , H01L21/31 , H01L21/318 , H01L21/336 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a method of depositing a SiNx layer and an a-Si layer on a thin film transistor(TFT) substrate at a sufficient deposition rate keeping high film quality. SOLUTION: A material layer near the interface of an a-Si layer is deposited at a low deposition rate, so as to be extremely high in quality, and a material layer distant from the interface is deposited at a high deposition rate to be somewhat lower in quality than the former material layer but sufficiently high in quality. Through this method, a g-SiNx film 54 which is of high quality and deposited at a low deposition rate is deposited on the top surface of a g-SiNx film 52, which is of average quality and deposited at a high deposition rate, and then an a-Si layer is deposited thereon, whereby a TFT of extremely high quality can be efficiently manufactured. At this point, an a-Si layer of high quality is deposited on a g-SiNx layer at a low deposition rate to form an interface 56, and an a-Si layer of average quality is deposited thereon at a high deposition rate to have the formation of an a-Si layer 58 completed. This method can be applied to an interface between an a-Si layer and an active semiconductor layer, and the method can be also applied to a back channel type or an etching stop type TFT.

5. 发明专利

AT101879T 未知
公开(公告)号：AT101879T
公开(公告)日：1994-03-15
申请号：AT87311193
申请日：1987-12-18
申请人： APPLIED MATERIALS INC
发明人： WANG DAVID NIN-KOU , WHITE JOHN M , LAW KAM S , LEUNG CISSY , UMOTOY SALVADOR P , COLLINS KENNETH S , ADAMIK JOHN A , PERLOV ILYA , MAYDAN DAN
IPC分类号： C23C16/48 , C23C16/04 , C23C16/40 , C23C16/42 , C23C16/44 , C23C16/455 , C23C16/46 , C23C16/50 , C23C16/509 , C23C16/54 , C23F4/00 , C30B25/14 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/683
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor (10) is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor (16) and wafer fingers (20) which collectively remove the wafer (15) from a robot transfer blade (24) and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold (26) then return the wafer to the blade. A combined RF/gas feed-through device (36) protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold (26) is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust fases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressure including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone on in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

6. 发明专利

DE69323716D1 未知
公开(公告)号：DE69323716D1
公开(公告)日：1999-04-08
申请号：DE69323716
申请日：1993-12-24
申请人： APPLIED MATERIALS INC
发明人： LAW KAM S , ROBERTSON ROBERT , LOU PAMELA , KOLLRACK MARC MICHAEL , LEE ANGELA , MAYDAN DAN
IPC分类号： H01L21/205 , C23C16/24 , C23C16/34 , C23C16/54 , H01L21/00 , H01L21/31 , H01L21/336 , H01L29/786 , C23C16/44 , H01L21/84

7. 发明专利

DE3789142D1 未知
公开(公告)号：DE3789142D1
公开(公告)日：1994-03-31
申请号：DE3789142
申请日：1987-12-18
申请人： APPLIED MATERIALS INC
发明人： WANG DAVID NIN-KOU , WHITE JOHN M , LAW KAM S , LEUNG CISSY , UMOTOY SALVADOR P , COLLINS KENNETH S , ADAMIK JOHN A , PERLOV ILYA , MAYDAN DAN
IPC分类号： C23C16/48 , C23C16/04 , C23C16/40 , C23C16/42 , C23C16/44 , C23C16/455 , C23C16/46 , C23C16/50 , C23C16/509 , C23C16/54 , C23F4/00 , C30B25/14 , H01L21/205 , H01L21/302 , H01L21/3065 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/683
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor (10) is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor (16) and wafer fingers (20) which collectively remove the wafer (15) from a robot transfer blade (24) and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold (26) then return the wafer to the blade. A combined RF/gas feed-through device (36) protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold (26) is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust fases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressure including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone on in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

8. 发明专利

JP2003178993A METHOD OF CONDITIONING CVD CHAMBER AFTER CLEANING THEREOF 审中-公开
公开(公告)号：JP2003178993A
公开(公告)日：2003-06-27
申请号：JP2002359616
申请日：2002-12-11
申请人： APPLIED MATERIALS INC
发明人： ROBERTSON ROBERT , KOLLRACK MICHAEL , LEE ANGELA , TAKEHARA TAKAKO , FENG GUOFU JEFF , SHANG QUANYUAN , LAW KAM S
IPC分类号： C23C16/44 , H01L21/205
摘要： PROBLEM TO BE SOLVED: To effectively remove residual substance of fluorine and particles from a CVD chamber. SOLUTION: Multiple processes are used, after the cleaning, to adjust a chemical evaporation chamber during the subsequent deposition process. This multiple processes are executed by removing the residual substance of fluorine from the chamber with hydrogen plasma and subsequently depositing a solid state compound within the chamber to pack the particles remaining within the chamber. COPYRIGHT: (C)2003,JPO

9. 发明专利

JP2002151496A MULTIPLE FREQUENCY PLASMA CHAMBER WITH GROUNDING CAPACITOR AT CATHODE 失效
公开(公告)号：JP2002151496A
公开(公告)日：2002-05-24
申请号：JP2001136357
申请日：2001-05-07
申请人： APPLIED MATERIALS INC
发明人： SHEN SAN , JEFF C OLSEN , YADAV SANJAY , SHANG QUANYUAN , LAW KAM S
IPC分类号： H05H1/46 , B01J19/08 , C23C16/34 , C23C16/509 , C23C16/52 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and a method for manufacturing an electronic workpiece in which first and second electrodes within a plasma chamber are respectively connected to low frequency and high frequency RF power supplies. SOLUTION: At least one of capacitors 50-54 is connected between the first electrode and electrical ground. The one or more capacitors can reduce or eliminate the coupling of high frequency RF output to any plasma outside the region directly between the two electrodes 12 and 20. Consequently, the chamber can improve plasma processing performance by concentrating more of the RF output in the region between the two electrodes.

10. 发明专利

JP2002033289A FLUORINE PROCESS FOR CLEANING SEMICONDUCTOR PROCESS CHAMBER 失效
公开(公告)号：JP2002033289A
公开(公告)日：2002-01-31
申请号：JP2001090297
申请日：2001-03-27
申请人： APPLIED MATERIALS INC
发明人： HARUHIRO HARRY GOTO , WILLIAM R HIRSCHBERGER , SHANG QUANYUAN , LAW KAM S
IPC分类号： B08B5/00 , B08B7/00 , C23C16/44 , H01L21/02 , H01L21/205 , H01L21/302 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To provide a method for cleaning a semiconductor process chamber using molecular fluorine (F2) gas as a principal precursor reagent. SOLUTION: In this method, residue is eliminated from the interior of the semiconductor process chamber, using molecular fluorine (F2) gas as the principal precursor reagent. In one embodiment, a portion of the molecular fluorine is decomposed by a plasma, atomic fluorine is formed, and the resulting mixture gas of atomic fluorine and molecular fluorine is supplied to the chamber whose interior is to be cleaned. In another embodiment, the molecular fluorine gas cleans the inside of the semiconductor process chamber without any plasma excitation. Molecular fluorine gas has the advantage of not being a global warming gas, unlike fluorine-containing gas compounds which are used conventionally for chamber cleaning, such as NF3, C2F6 and SF6.

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