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1. 发明授权

US11489110B2 Methods for treating magnesium oxide film 有权
公开(公告)号：US11489110B2
公开(公告)日：2022-11-01
申请号：US16845600
申请日：2020-04-10
申请人： APPLIED MATERIALS, INC.
发明人： Xiaodong Wang , Renu Whig , Jianxin Lei , Rongjun Wang
IPC分类号： H01L43/12 , H01L43/10 , C23C14/08
摘要： A method of forming a tunnel layer of a magnetoresistive random-access memory (MRAM) structure includes forming a first magnesium oxide (MgO) layer by sputtering an MgO target using radio frequency (RF) power, exposing the first MgO layer to oxygen for approximately 5 seconds to approximately 20 seconds at a flow rate of approximately 10 sccm to approximately 15 sccm, and forming a second MgO layer on the first MgO layer by sputtering the MgO target using RF power. The method may be performed after periodic maintenance of a process chamber to increase the tunnel magnetoresistance (TMR) of the tunnel layer.

2. 发明授权

US11227751B1 Plasma chamber target for reducing defects in workpiece during dielectric sputtering 有权
公开(公告)号：US11227751B1
公开(公告)日：2022-01-18
申请号：US16918513
申请日：2020-07-01
申请人： APPLIED MATERIALS, INC.
发明人： Xiaodong Wang , Jianxin Lei , Rongjun Wang
IPC分类号： H01J37/34 , C23C14/34
摘要： Methods and apparatus for plasma chamber target for reducing defects in workpiece during dielectric sputtering are provided. For example, a dielectric sputter deposition target can comprise a dielectric compound having a predefined average grain size ranging from approximately 65 μm to 500 μm, wherein the dielectric compound is at least one of magnesium oxide or aluminum oxide.

3. 发明授权

US10770346B2 Selective cobalt removal for bottom up gapfill 有权
公开(公告)号：US10770346B2
公开(公告)日：2020-09-08
申请号：US16229710
申请日：2018-12-21
申请人： Applied Materials, Inc.
发明人： Xikun Wang , Jianxin Lei , Nitin Ingle , Roey Shaviv
IPC分类号： H01L21/302 , H01L21/461 , H01L21/4763 , H01L21/285 , H01L21/3213 , H01L21/768 , H01L21/67 , H01L23/532 , H01L21/321
摘要： Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The exposed region of cobalt may include an overhang of cobalt on a trench defined on a substrate. The plasma effluents may produce cobalt chloride at the overhang of cobalt. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the overhang of cobalt.

4. 发明申请

US20200235104A1 Cap Layer For Bit Line Resistance Reduction 审中-公开
公开(公告)号：US20200235104A1
公开(公告)日：2020-07-23
申请号：US16839392
申请日：2020-04-03
申请人： Applied Materials, Inc.
发明人： Priyadarshi Panda , Jianxin Lei , Wenting Hou , Mihaela Balseanu , Ning Li , Sanjay Natarajan , Gill Yong Lee , In Seok Hwang , Nobuyuki Sasaki , Sung-Kwan Kang
IPC分类号： H01L27/108 , H01L21/3213 , H01L21/033
摘要： Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

5. 发明申请

US20190088540A1 METHODS AND APPARATUS FOR FILLING SUBSTRATE FEATURES WITH COBALT 审中-公开
公开(公告)号：US20190088540A1
公开(公告)日：2019-03-21
申请号：US15711169
申请日：2017-09-21
申请人： APPLIED MATERIALS, INC.
发明人： Wenting Hou , Jianxin Lei , Joung Joo Lee , Rong Tao
IPC分类号： H01L21/768 , C23C16/06 , C23C14/14
摘要： Methods and apparatus for filling features with cobalt are provided herein. In some embodiments, a method for processing a substrate includes: depositing a first cobalt layer via a chemical vapor deposition (CVD) process atop a substrate and within a feature disposed in the substrate; and at least partially filling the feature with cobalt or cobalt containing material by performing a plasma process in a physical vapor deposition (PVD) chamber having a cobalt target to reflow a portion of the first cobalt layer into the feature. The PVD chamber may be configured to simultaneously deposit cobalt or cobalt containing material within the feature from a cobalt target disposed in the PVD chamber.

6. 发明授权

US09461137B1 Tungsten silicide nitride films and methods of formation 有权
标题翻译：钨硅化钨薄膜及其形成方法
公开(公告)号：US09461137B1
公开(公告)日：2016-10-04
申请号：US14938559
申请日：2015-11-11
申请人： APPLIED MATERIALS, INC.
发明人： Jothilingam Ramalingam , Rajkumar Jakkaraju , Jianxin Lei , Zhiyong Wang
IPC分类号： H01L21/336 , H01L29/49 , H01L21/285 , H01L21/28
CPC分类号： H01L29/4975 , C23C14/0036 , C23C14/022 , C23C14/0641 , C23C14/5826 , H01L21/28088 , H01L21/28097 , H01L21/28202 , H01L21/2855
摘要： Embodiments of the present disclosure include tungsten silicide nitride films and methods for depositing tungsten silicide nitride films. In some embodiments, a thin film microelectronic device includes a semiconductor substrate having a tungsten gate electrode stack comprising a tungsten silicide nitride film having a formula WxSiyNz, wherein x is about 19 to about 22 atomic percent, y is about 57 to about 61 atomic percent, and z is about 15 to about 20 atomic percent. In some embodiments, a method of processing a substrate disposed in physical vapor deposition (PVD) chamber, includes: exposing a substrate having a gate insulating layer to a plasma formed from a first process gas comprising nitrogen and argon; sputtering silicon and tungsten material from a target disposed within a processing volume of the PVD chamber; depositing atop the gate insulating layer a tungsten silicide nitride layer as described above; and depositing a bulk tungsten layer atop the tungsten silicide nitride layer.
摘要翻译：本公开的实施例包括硅化钨氮化物膜和用于沉积硅化钨氮化物膜的方法。在一些实施例中，薄膜微电子器件包括具有钨栅极电极堆叠的半导体衬底，所述钨栅电极堆叠包括具有式W x Si y N z的硅化钨化硅膜，其中x为约19至约22原子％，y为约57至约61原子％，z为约15〜约20原子％。在一些实施例中，处理设置在物理气相沉积（PVD）室中的衬底的方法包括：将具有栅极绝缘层的衬底暴露于由包括氮和氩的第一工艺气体形成的等离子体; 从设置在PVD室的处理容积内的靶溅射硅和钨材料; 在栅极绝缘层的顶上沉积如上所述的硅化钨化硅层; 以及在硅化钨化硅层顶上沉积体钨层。

7. 发明授权

US11626410B2 Silicon-containing layer for bit line resistance reduction 有权
公开(公告)号：US11626410B2
公开(公告)日：2023-04-11
申请号：US17861412
申请日：2022-07-11
申请人： Applied Materials, Inc.
发明人： Tom Ho Wing Yu , Nobuyuki Sasaki , Jianxin Lei , Wenting Hou , Rongjun Wang , Tza-Jing Gung
IPC分类号： H01L27/108
摘要： Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

8. 发明授权

US10734235B2 Systems and methods for low resistivity physical vapor deposition of a tungsten film 有权
公开(公告)号：US10734235B2
公开(公告)日：2020-08-04
申请号：US16052135
申请日：2018-08-01
申请人： APPLIED MATERIALS, INC.
发明人： Jothilingam Ramalingam , Thanh X. Nguyen , Zhiyong Wang , Jianxin Lei , Xianmin Tang
IPC分类号： H01L21/285 , C23C14/18 , C23C14/34 , C23C14/35 , C23C14/56 , H01J37/34 , H01L21/326
摘要： Systems and methods for sputtering a layer of refractory metal layer onto a barrier layer disposed on a substrate are disclosed herein. In one or more embodiments, a method of sputter depositing a tungsten structure in an integrated circuit includes: moving a substrate into a plasma processing chamber and onto a substrate support in opposition to a sputter target assembly comprising a tungsten target having no more than ten parts per million of carbon and no more than ten parts per million of oxygen present as impurities; flowing krypton into the plasma processing chamber; and exciting the krypton into a plasma to deposit, by sputtering, a tungsten film layer on a material layer of a substrate supported by the substrate support. In some embodiments, the target assembly further includes a titanium backing plate and an aluminum bonding layer disposed between the titanium backing plate and the tungsten target.

9. 发明授权

US10388532B2 Methods and devices using PVD ruthenium 有权
公开(公告)号：US10388532B2
公开(公告)日：2019-08-20
申请号：US15718412
申请日：2017-09-28
申请人： Applied Materials, Inc.
发明人： Jothilingam Ramalingam , Ross Marshall , Jianxin Lei , Xianmin Tang
IPC分类号： H01L21/285 , H01L29/49 , H01L21/02 , H01L29/66 , H01L21/786 , H01L29/78 , C23C14/14 , C23C14/58 , C23C14/50 , C23C14/34 , H01L21/768 , C23C14/18 , C23C14/35 , H01L21/683
摘要： Ruthenium containing gate stacks and methods of forming ruthenium containing gate stacks are described. The ruthenium containing gate stack comprises a polysilicon layer on a substrate; a silicide layer on the polysilicon layer; a barrier layer on the silicide layer; a ruthenium layer on the barrier layer; and a spacer layer comprising a nitride on sides of the ruthenium layer, wherein the ruthenium layer comprises substantially no ruthenium nitride after formation of the spacer layer. Forming the ruthenium layer comprises sputtering the ruthenium in a krypton environment on a high current electrostatic chuck comprising a high resistivity ceramic material. The sputtered ruthenium layer is annealed at a temperature greater than or equal to about 500° C.

10. 发明申请

US20190122923A1 SELECTIVE COBALT REMOVAL FOR BOTTOM UP GAPFILL 审中-公开
公开(公告)号：US20190122923A1
公开(公告)日：2019-04-25
申请号：US16229710
申请日：2018-12-21
申请人： Applied Materials, Inc.
发明人： Xikun Wang , Jianxin Lei , Nitin Ingle , Roey Shaviv
IPC分类号： H01L21/768 , H01L21/67 , H01L21/3213 , H01L21/321 , H01L23/532
摘要： Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The exposed region of cobalt may include an overhang of cobalt on a trench defined on a substrate. The plasma effluents may produce cobalt chloride at the overhang of cobalt. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the overhang of cobalt.

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