专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11100013B2 Scheduling of read and write memory access requests 有权
公开(公告)号：US11100013B2
公开(公告)日：2021-08-24
申请号：US16058647
申请日：2018-08-08
申请人： Apple Inc.
发明人： Shane J. Keil
IPC分类号： G06F3/06 , G06F13/16 , G11C11/406 , G06F9/30 , G11C7/10 , G11C7/22
摘要： A memory system includes a memory circuit including a plurality of pages, including a particular page having a page activation time. The memory system also includes a memory controller circuit configured to receive a memory access request corresponding to data of the particular page. The memory controller circuit is also configured to transmit, in response to a determination that the particular page is inactive, an activation command to the memory circuit to activate the particular page, and to schedule a future transmission of an initial memory command for the particular page based on the page activation time.

2. 发明授权

US10621115B2 System and method for communication link management in a credit-based system 有权
公开(公告)号：US10621115B2
公开(公告)日：2020-04-14
申请号：US16024063
申请日：2018-06-29
申请人： Apple Inc.
发明人： Gregory S. Mathews , Shane J. Keil , Lakshmi Narasimha Nukala
IPC分类号： G06F13/16 , G06F15/17 , G06F15/167 , G06F13/40
CPC分类号： G06F13/1663 , G06F13/4022 , G06F15/167 , G06F15/17
摘要： A system and method for communication link management in a credit-based system is disclosed. In one embodiment, a system includes first and second functional circuit blocks implemented on an integrated circuit and being able to communicate with one another through establishment of source synchronous links. The first functional circuit block includes a write queue for storing data and information regarding write requests sent from the second functional circuit block. The write queue includes credit management circuitry arranged to convey one or more credits to the second functional circuit block responsive to receiving one or more write requests therefrom. Responsive to receiving the one or more credits and in the absence of any pending additional requests, the second functional circuit block may deactivate a link with the first functional circuit block.

3. 发明申请

US20200081622A1 MEMORY ACCESS SCHEDULING USING CATEGORY ARBITRATION 审中-公开
公开(公告)号：US20200081622A1
公开(公告)日：2020-03-12
申请号：US16565386
申请日：2019-09-09
申请人： Apple Inc.
发明人： Gregory S. Mathews , Shane J. Keil , Sukalpa Biswas , Lakshmi Narasimha Murthy Nukala , Thejasvi Magudilu Vijavaraj
IPC分类号： G06F3/06
摘要： A memory controller circuit coupled to a memory circuit that includes multiple banks may receive multiple access requests including a particular access request to a particular bank of the plurality of banks. The particular access request is associated with a particular virtual channel of a plurality of virtual channels. The memory controller circuit may select a given access requests of the multiple access requests based on an arbitration category value associated with a virtual channel of the given access request and modify the arbitration category value in response to selecting the given access request.

4. 发明授权

US09645630B2 Selectively permitting an apparatus to be awakened depending on a programmable setting 有权
公开(公告)号：US09645630B2
公开(公告)日：2017-05-09
申请号：US13745731
申请日：2013-01-18
申请人： Apple Inc.
发明人： Shane J. Keil , Erik P. Machnicki , Josh P. de Cesare
IPC分类号： G06F1/00 , G06F9/00 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203
摘要： Techniques are disclosed relating to power management within an integrated circuits. In one embodiment an apparatus is disclosed that includes a circuit and a power management unit. The power management unit is configured to provide, based on a programmable setting, an indication of whether an attempted communication to the circuit is permitted to cause the circuit to exit from a power-managed state. In some embodiments, the apparatus includes a fabric configured to transmit the attempted communication to the circuit from a device. In such an embodiment, the circuit is configured to exit the power-managed state in response to receiving the attempted communication. The fabric is configured to determine whether to transmit the attempted communication based on the indication provided by the power management unit.

5. 发明授权

US09438256B2 Slow to fast clock synchronization 有权
标题翻译：慢到快时钟同步
公开(公告)号：US09438256B2
公开(公告)日：2016-09-06
申请号：US14478387
申请日：2014-09-05
申请人： Apple Inc.
发明人： Shane J. Keil , Gilbert H. Herbeck
IPC分类号： H03L7/00 , H03L7/091 , H03K5/1534
CPC分类号： H03L7/091 , H03K5/1534
摘要： A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal.
摘要翻译：用于将从第一时钟域到第二时钟域的数据传输同步的方法和装置包括从包括在第一时钟域中的电路的采样数据。然后可以将来自第一时钟域的时钟信号与来自第二时钟域的时钟信号同步。然后可以利用来自第二时钟域的时钟信号来捕获采样数据，以响应于同步的第一时钟信号的边沿的检测。

6. 发明授权

US09354658B2 Method for asynchronous gating of signals between clock domains 有权
标题翻译：时钟域之间信号异步门控的方法
公开(公告)号：US09354658B2
公开(公告)日：2016-05-31
申请号：US14468982
申请日：2014-08-26
申请人： Apple Inc.
发明人： Erik P. Machnicki , Shane J. Keil
IPC分类号： G06F1/12 , H03K5/01 , H03K5/00
CPC分类号： G06F1/12 , H03K5/01 , H03K2005/00013
摘要： An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.
摘要翻译：公开了一种用于将来自第一时钟域的信号同步到第二时钟域的装置。该装置可以包括电路，同步电路和时钟门电路。电路可以取决于第一时钟信号取消置位第一使能信号。同步电路可以产生与第二时钟信号同步的第二使能信号，并且可以响应于取消断言第一使能信号来取消断言第二使能信号。时钟门电路可以产生取决于第二时钟信号的第三时钟信号，并且可以响应于取消断言第二使能信号来禁用第三时钟信号。所述电路还可以响应于确定从所述第一使能信号解除所述已经经过的预定时间段来禁止所述第二时钟信号。

7. 发明申请

US20160026234A1 Interfacing Dynamic Hardware Power Managed Blocks and Software Power Managed Blocks 审中-公开
标题翻译：动态硬件电源管理块和软件电源管理块的接口
公开(公告)号：US20160026234A1
公开(公告)日：2016-01-28
申请号：US14876922
申请日：2015-10-07
申请人： Apple Inc.
发明人： Erik P. Machnicki , Gurjeet S. Saund , Munetoshi Fukami , Shane J. Keil , Chaitanya Kosaraju , Erdem Guleyupoglu , Jason M. Kassoff , Kevin C. Wong
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/3206 , G06F1/3246 , G06F1/329 , G06F1/3293 , Y02D10/24 , Y02D50/20
摘要： A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.
摘要翻译：公开了用于接口动态硬件功率管理块和软件功率管理块的方法和装置。在一个实施例中，集成电路（IC）可以包括多个功率可管理的功能单元。功能单元可以通过硬件，软件或两者进行功率管理。每个功能单元可以通过直接通信链路耦合到至少一个其它功能单元。链路状态机可以监视功能单元之间的每个通信链路，并且可以将链路可用性的指示广播到耦合到链路的功能单元。响应于关闭给定链路的软件请求或耦合到链路的功能单元之一的硬件启动关机，链路状态机可以广播并指示链路不可用。

8. 发明申请

US20150347287A1 System on a Chip with Always-On Processor Which Reconfigures SOC and Supports Memory-Only Communication Mode 有权
标题翻译：使用永久处理器的芯片上的系统重新配置SOC并支持仅内存通信模式
公开(公告)号：US20150347287A1
公开(公告)日：2015-12-03
申请号：US14458949
申请日：2014-08-13
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. De Cesare , Anand Dalal
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
摘要翻译：在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。在一些实施例中，组件可以被配置为唤醒SOC内的存储器控制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

9. 发明申请

US20150323960A1 METHOD FOR ASYNCHRONOUS GATING OF SIGNALS BETWEEN CLOCK DOMAINS 有权
标题翻译：用于时钟域之间信号异步增益的方法
公开(公告)号：US20150323960A1
公开(公告)日：2015-11-12
申请号：US14468982
申请日：2014-08-26
申请人： Apple Inc.
发明人： Erik P. Machnicki , Shane J. Keil
IPC分类号： G06F1/12 , H03K5/01
CPC分类号： G06F1/12 , H03K5/01 , H03K2005/00013
摘要： An apparatus for synchronizing a signal from a first clock domain into a second clock domain is disclosed. The apparatus may include circuitry, a synchronization circuit, and a clock gate circuit. The circuitry may de-assert a first enable signal dependent upon a first clock signal. The synchronization circuit may generate a second enable signal synchronized to a second clock signal and may de-assert the second enable signal in response to de-asserting the first enable signal. The clock gate circuit may generate a third clock signal dependent upon the second clock signal, and may disable the third clock signal responsive to de-asserting the second enable signal. The circuitry may further disable the second clock signal in response to determining a predetermined period of time has elapsed since de-asserting the first enable signal.
摘要翻译：公开了一种用于将来自第一时钟域的信号同步到第二时钟域的装置。该装置可以包括电路，同步电路和时钟门电路。电路可以取决于第一时钟信号取消置位第一使能信号。同步电路可以产生与第二时钟信号同步的第二使能信号，并且可以响应于取消断言第一使能信号来取消断言第二使能信号。时钟门电路可以产生取决于第二时钟信号的第三时钟信号，并且可以响应于取消断言第二使能信号来禁用第三时钟信号。所述电路还可以响应于确定从所述第一使能信号解除所述已经经过的预定时间段来禁止所述第二时钟信号。

10. 发明公开

US20240061617A1 Memory Bank Hotspotting 审中-公开
公开(公告)号：US20240061617A1
公开(公告)日：2024-02-22
申请号：US18497883
申请日：2023-10-30
申请人： Apple Inc.
发明人： Gregory S. Mathews , Kai Lun Hsiung , Lakshmi Narasimha Murthy Nukala , Shane J. Keil , Thejasvi Magudilu Vijayaraj , Yanzhe Liu , Tao Zhang
IPC分类号： G06F3/06 , G06F13/16
CPC分类号： G06F3/0659 , G06F3/0611 , G06F13/1605 , G06F3/0644 , G06F3/0673
摘要： Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式