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    • 2. 发明申请
    • BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER
    • 从眼睛观察器接收串行数据信号的位错误率检查器
    • WO2012037517A2
    • 2012-03-22
    • PCT/US2011052028
    • 2011-09-16
    • ALTERA CORPDING WEIQIPAN MINGDELI PENGSHUMARAYEV SERGEYSHIMANOUCHI MASASHI
    • DING WEIQIPAN MINGDELI PENGSHUMARAYEV SERGEYSHIMANOUCHI MASASHI
    • H04L1/00G01R29/02
    • H04L1/203G01R31/3171
    • An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.
    • 提供了一种IC,其包括耦合到眼睛观察者的眼睛观察器和BER检查器,其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中,BER检查器从眼睛观察器接收串行数据信号,而不经过串行数据信号通过解串器。 在一个实现中,BER检验器将串行数据信号与参考数据信号进行比较,以确定串行数据信号的BER。 在一个实现中,IC包括耦合到眼睛观察器和BER检查器的IC核心,其中BER检验器在IC核心之外。 在一个实现中,BER检查器是专用的BER检查器。 在一个实现中,BER检查器包括异或门,耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。
    • 3. 发明申请
    • SIMULATION TOOL FOR HIGH-SPEED COMMUNICATIONS LINKS
    • 高速通信链接的仿真工具
    • WO2011133565A2
    • 2011-10-27
    • PCT/US2011033071
    • 2011-04-19
    • ALTERA CORPLI PENGSHIMANOUCHI MASASHITRAN THUNGOC MSHUMARAYEV SERGEY
    • LI PENGSHIMANOUCHI MASASHITRAN THUNGOC MSHUMARAYEV SERGEY
    • G06F9/455G06F11/25G06F17/50
    • G06F17/5009G06F17/5036G06F2217/10
    • A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two- dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.
    • 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统,例如发射(TX)电路,接收(TX)电路,向TX和RX电路提供参考时钟信号的振荡器电路,以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括诸如传递函数,概率密度函数和眼睛特征的特征函数。 链接仿真工具可以具有能够执行二维(双变量)卷积运算并且对由行为模型提供的特征函数应用双域(频率 - 时间)变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。
    • 5. 发明公开
    • BIT ERROR RATE CHECKER RECEIVING SERIAL DATA SIGNAL FROM AN EYE VIEWER
    • BITFEHLERRATENPRÜFERZUM EMPFANG SERIELLER DATENSIGNALE VON EINEMSICHTGERÄT
    • EP2617149A4
    • 2013-09-04
    • EP11826056
    • 2011-09-16
    • ALTERA CORP
    • DING WEIQIPAN MINGDELI PENGSHUMARAYEV SERGEISHIMANOUCHI MASASHI
    • H04L1/20G01R29/02G01R31/3181
    • H04L1/203G01R31/3171
    • An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.
    • 提供了包括眼睛观察器和耦合到眼睛观察器的BER检查器的IC,其中BER检查器从眼睛观察器接收串行数据信号。 在一个实现中,BER检查器接收来自观看者的串行数据信号,而串行数据信号不经过解串器。 在一个实现中,BER检查器将串行数据信号与参考数据信号进行比较以确定串行数据信号的BER。 在一个实现中,IC包括耦合到眼睛观察器和BER检查器的IC内核,其中BER检查器在IC内核之外。 在一个实现中,BER检查器是专用的BER检查器。 在一个实现中,BER检查器包括异或门,耦合到异或门的可编程延迟电路以及耦合到异或门的错误计数器。