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1. 发明申请

WO2010102019A1 METHOD AND APPARATUS FOR SYSTEM TESTING USING SCAN CHAIN DECOMPOSITION 审中-公开
标题翻译：使用扫描链分解的系统测试的方法和装置
公开(公告)号：WO2010102019A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026072
申请日：2010-03-03
申请人： ALCATEL-LUCENT USA INC. , ALCATEL-LUCENT IRELAND LTD , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
发明人： GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558
摘要： A method is provided for testing a portion of a system under test via a scan chain of the system under test. The method includes decomposing the scan chain into a plurality of segments, generating a set of instructions for testing the portion of the system under test, and executing the set of instructions for testing the portion of the system under test. The scan chain is composed of a plurality of elements, and each segment includes at least one of the elements of the scan chain. The set of instructions includes a plurality of processor instructions associated with an Instruction Set Architecture (ISA), and a plurality of test instructions. The test instructions include, for each of the plurality of segments of the scan chain, at least one scan operation to be performed on the segment. An associated apparatus also is provided.
摘要翻译：提供了一种用于通过被测系统的扫描链测试待测系统的一部分的方法。该方法包括将扫描链分解成多个段，产生一组用于测试被测系统的部分的指令，以及执行用于测试被测系统部分的一组指令。扫描链由多个元件组成，并且每个片段包括扫描链的元件中的至少一个元件。所述指令集包括与指令集架构（ISA）相关联的多个处理器指令以及多个测试指令。对于扫描链的多个片段中的每一个，测试指令包括要在片段上执行的至少一个扫描操作。还提供了一种相关联的装置。

2. 发明申请

WO2011159598A1 METHOD AND APPARATUS FOR PROVIDING SCAN CHAIN SECURITY 审中-公开
标题翻译：提供扫描链安全的方法和装置
公开(公告)号：WO2011159598A1
公开(公告)日：2011-12-22
申请号：PCT/US2011/040152
申请日：2011-06-13
申请人： ALCATEL-LUCENT USA INC. , ALCATEL LUCENT , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
发明人： GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
IPC分类号： G01R31/3185 , G01R31/317
CPC分类号： G01R31/31719 , G01R31/318572
摘要： A scan chain security capability is provided herein. The scan chain security capability enables secure control over normal use of a scan chain of a system, e.g., for purposes such as testing prior to deployment or sale of the system, in-field testing after deployment or sale of the system, in-field modification of the system, and the like. The scan chain security capability enables secure control over normal use of a scan chain by enabling control over interruption of a scan chain and re-establishment of an interrupted scan chain. A scan chain security component is configured for removing an open- circuit condition from the scan chain in response to a control signal. The control signal may be generated in response to validation of a security key, in response to successful completion of a challenge-based authentication process, or in response to any other suitable validation or authentication. The scan chain security component also may be configured for creating an open- circuit condition in the scan chain in response to a second control signal. The second control signal may be a scan register value received via the scan chain.
摘要翻译：本文提供扫描链安全功能。扫描链安全功能可以对系统的扫描链的正常使用进行安全控制，例如，用于系统部署或销售前的测试，部署或销售系统后的现场测试，现场系统的修改等。扫描链安全功能可以通过启用对扫描链的中断控制和重新建立中断的扫描链的安全控制扫描链的正常使用。扫描链安全组件被配置为响应于控制信号从扫描链中去除开路状况。响应于成功完成基于挑战的认证过程，或者响应于任何其他合适的验证或认证，可以响应于安全密钥的验证而产生控制信号。扫描链安全组件还可以被配置为响应于第二控制信号在扫描链中创建开路状态。第二控制信号可以是经由扫描链接收的扫描寄存器值。

3. 发明申请

WO2010101984A1 METHOD AND APPARATUS FOR SYSTEM TESTING USING MULTIPLE INSTRUCTION TYPES 审中-公开
标题翻译：使用多种指令类型进行系统测试的方法和装置
公开(公告)号：WO2010101984A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026022
申请日：2010-03-03
申请人： ALCATEL-LUCENT USA INC. , ALCATEL-LUCENT IRELAND LTD , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
发明人： GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558
摘要： An apparatus for use in testing at least a portion of a system under test via a Test Access Port (TAP) is provided. The apparatus includes a memory for storing a set of instructions of a test instruction set architecture and a processor executing the set of instructions of the test instruction set architecture for testing at least a portion of the system under test via the TAP. The set of instructions of the test instruction set architecture includes a first set of instructions including a plurality of instructions of an Instruction Set Architecture (ISA) supported by the processor and a second set of instructions including a plurality of test instructions associated with the TAP. The instructions of the first set of instructions and the instructions of the second set of instructions are integrated to form the set of instructions of the test instruction set architecture.
摘要翻译：提供了一种用于通过测试访问端口（TAP）测试被测系统的至少一部分的装置。该装置包括存储器，用于存储测试指令集体系结构的一组指令，以及执行测试指令集体系结构指令集的处理器，用于经由TAP测试待测系统的至少一部分。测试指令集架构的指令集包括第一组指令，其包括由处理器支持的指令集架构（ISA）的多个指令，以及包括与该TAP相关联的多个测试指令的第二组指令。第一组指令和第二组指令的指令的指令被集成以形成测试指令集架构的指令集。

4. 发明申请

WO2012005895A1 METHOD AND APPARATUS FOR VIRTUAL IN-CIRCUIT EMULATION 审中-公开
标题翻译：虚拟电路仿真的方法和装置
公开(公告)号：WO2012005895A1
公开(公告)日：2012-01-12
申请号：PCT/US2011/040420
申请日：2011-06-15
申请人： ALCATEL-LUCENT USA INC. , ALCATEL-LUCENT , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
发明人： GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
IPC分类号： G01R31/3185
CPC分类号： G01R31/318544 , G01R31/3177 , G01R31/318558 , G01R31/318572
摘要： A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches). The Virtual ICE Driver is configured for receiving a plurality of scan segment operations generated by a plurality of target ICE controllers of at least one ICE host, scheduling the received scan segment operations, based at least in part on a scan chain of the target hardware, to form thereby a scheduled set of scan segment operations, and providing the scheduled set of scan segment operations to a processor configured for executing the scheduled set of scan segment operations for testing the target hardware.
摘要翻译：本文提供虚拟在线仿真（ICE）能力，用于支持联合测试动作组（JTAG）硬件的测试。虚拟ICE驱动程序被配置为使得任何调试软件能够以灵活和可扩展的方式与目标硬件进行接口。配置虚拟ICE驱动程序，使得与虚拟ICE驱动程序一起使用的测试指令集不需要计算向量，因为JTAG操作在扫描段上表示为本地本地指令，从而可以直接访问ICE资源。虚拟ICE驱动器被配置为使得ICE可以与基于仪器的JTAG方法（例如，IEEE P1687标准和其他合适的方法）组合。虚拟ICE驱动器被配置为用于接收由至少一个ICE主机的多个目标ICE控制器产生的多个扫描段操作，至少部分地基于目标硬件的扫描链来调度所接收的扫描段操作，从而形成预定的一组扫描段操作，以及将调度的扫描段操作集合提供给被配置为执行用于测试目标硬件的预定扫描段操作集合的处理器。

5. 发明申请

WO2010101995A1 METHOD AND APPARATUS FOR SYSTEM TESTING USING MULTIPLE PROCESSORS 审中-公开
标题翻译：使用多个处理器进行系统测试的方法和装置
公开(公告)号：WO2010101995A1
公开(公告)日：2010-09-10
申请号：PCT/US2010/026037
申请日：2010-03-03
申请人： ALCATEL-LUCENT USA INC. , ALCATEL-LUCENT IRELAND LTD. , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
发明人： GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford
IPC分类号： G01R31/3185
CPC分类号： G01R31/318558
摘要： An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.
摘要翻译：提供了一种用于经由被配置为访问被测系统的测试访问端口（TAP）来对待测系统的至少一部分进行测试的装置。该装置包括：第一处理器，用于执行适于经由TAP控制被测系统的至少一部分的测试的指令;以及第二处理器，用于支持与该TAP的接口。第一处理器被配置为在执行测试指令期间检测与TAP的控制相关联的TAP相关指令，并将TAP相关指令传播到第二处理器。第二处理器被配置用于接收由第一处理器检测到的TAP相关指令并处理TAP相关指令。第一处理器被配置为与第二处理器处理与TAP相关的指令同时执行至少一个任务。还提供了相关联的方法。

6. 发明申请

WO2009073100A1 METHOD AND APPARATUS FOR TESTING A SYSTEM-ON-CHIP INVOLVING PARALLEL AND SERIAL ACCESSES 审中-公开
标题翻译：用于测试涉及并行和串行访问的片上系统的方法和装置
公开(公告)号：WO2009073100A1
公开(公告)日：2009-06-11
申请号：PCT/US2008/013054
申请日：2008-11-24
申请人： ALCATEL-LUCENT USA INC. , CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
发明人： CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
IPC分类号： G06F11/26 , G01R31/3183
CPC分类号： G06F11/267 , G01R31/318533 , G06F11/27
摘要： The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system- on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system- on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.
摘要翻译：本发明提供了用于芯片级JTAG测试的新的硬件描述语言。被称为新BSDL（NSDL）的这种新的硬件描述语言使得能够描述片上系统的测试资源，从而能够以便于对系统级芯片进行测试的方式来描述片上系统，在芯片上。本发明提供了一种用于描述片上系统的自下而上的方法。本发明支持片上系统的每个组件的算法描述，并且支持片上系统的组件之间的互连的算法描述，从而能够产生整个系统的算法描述芯片或片上系统的部分。本发明支持对一个或多个片上系统设备的并行访问，包括用于描述和使用用于测试的并行访问的方法。

7. 发明申请

WO2009097098A1 APPARATUS AND METHOD FOR CONTROLLING DYNAMIC MODIFICATION OF A SCAN PATH 审中-公开
标题翻译：用于控制扫描路径动态修改的装置和方法
公开(公告)号：WO2009097098A1
公开(公告)日：2009-08-06
申请号：PCT/US2009/000453
申请日：2009-01-23
申请人： ALCATEL-LUCENT USA INC. , CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
发明人： CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
IPC分类号： G01R31/3185
CPC分类号： G01R31/318536 , G01R31/318558
摘要： The invention includes an apparatuses and associated methods for controlling dynamic modification of a testing scan path using a control scan path. In one embodiment, an apparatus includes a testing scan path and a control scan path. The testing scan path includes testing components and at least one hierarchy-enabling component. In one embodiment, the control scan path includes at least one control component coupled to the at least one hierarchy-enabling component for controlling dynamic modification of the testing scan path. In one embodiment, the control scan path includes the at least one hierarchy-enabling component, wherein the at least one hierarchy- enabling component is adapted for dynamically modifying the testing scan path using the control scan path. The dynamic modification of the testing scan path may include modifying a hierarchy of the testing scan path, such as selecting or deselecting one or more hierarchical levels of the testing scan path.
摘要翻译：本发明包括一种用于使用控制扫描路径来控制测试扫描路径的动态修改的装置和相关方法。在一个实施例中，装置包括测试扫描路径和控制扫描路径。测试扫描路径包括测试组件和至少一个层次结构启用组件。在一个实施例中，控制扫描路径包括耦合到所述至少一个层级使能部件的至少一个控制部件，用于控制测试扫描路径的动态修改。在一个实施例中，所述控制扫描路径包括所述至少一个层次化启用组件，其中所述至少一个层级使能组件适于使用所述控制扫描路径来动态地修改所述测试扫描路径。测试扫描路径的动态修改可以包括修改测试扫描路径的层次结构，诸如选择或取消选择测试扫描路径的一个或多个层级。

8. 发明申请

WO2009073120A1 METHOD AND APPARATUS FOR TESTING A SYSTEM-ON-CHIP INVOLVING PARALLEL AND SERIAL ACCESSES 审中-公开
标题翻译：用于测试涉及并行和串行访问的片上系统的方法和装置
公开(公告)号：WO2009073120A1
公开(公告)日：2009-06-11
申请号：PCT/US2008/013110
申请日：2008-11-25
申请人： ALCATEL-LUCENT USA INC. , CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
发明人： CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
IPC分类号： G06F11/26 , G01R31/3183
CPC分类号： G06F11/27 , G01R31/3177 , G01R31/318533 , G06F11/267
摘要： The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system- on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system- on-chip.
摘要翻译：本发明提供了用于芯片级JTAG测试的新的硬件描述语言。被称为新BSDL（NSDL）的这种新的硬件描述语言使得能够描述片上系统的测试资源，从而能够以便于对系统级芯片进行测试的方式来描述片上系统，在芯片上。本发明提供了一种用于描述片上系统的自下而上的方法。本发明支持片上系统的每个组件的算法描述，并且支持片上系统的组件之间的互连的算法描述，从而能够产生整个系统的算法描述芯片或片上系统的部分。

9. 发明申请

WO2009097088A1 APPARATUS AND METHOD FOR ISOLATING PORTIONS OF A SCAN PATH OF A SYSTEM-ON-CHIP 审中-公开
标题翻译：用于分离系统片上扫描路径的方法的装置和方法
公开(公告)号：WO2009097088A1
公开(公告)日：2009-08-06
申请号：PCT/US2009/000346
申请日：2009-01-21
申请人： ALCATEL-LUCENT USA INC. , CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
发明人： CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
IPC分类号： G01R31/3185
CPC分类号： G01R31/318544 , G01R31/318536
摘要： The invention includes an apparatus and method for dynamically isolating a portion of a scan path of a system-on-chip. In one embodiment, an apparatus includes a scan path and control logic. The scan path includes at least a first hierarchical level, where the first hierarchical level includes a plurality of components, and a second hierarchical level having at least one component. The second hierarchical level is adapted for being selected and deselected such that the second hierarchical level is active or inactive. The control logic is adapted to filter application of at least one control signal to the at least one component of the second hierarchical level in a manner for controlling propagation of data within the second hierarchical level independent of propagation of data within the first hierarchical level. In one embodiment, when the second hierarchical level is deselected, the control logic prevents data from being propagated within the second hierarchical level while data is propagated within the first hierarchical level. In one embodiment, the second hierarchical level may be used for independent, parallel testing while data continues to be propagated through the first hierarchical level.
摘要翻译：本发明包括一种用于动态隔离片上系统的扫描路径的一部分的装置和方法。在一个实施例中，一种装置包括扫描路径和控制逻辑。扫描路径至少包括第一层级，其中第一层级包括多个组件，以及具有至少一个组件的第二层级。第二层级适于被选择和取消选择，使得第二层次级别是活动的或不活动的。控制逻辑适用于以与第一层次级别内的数据的传播无关地控制第二层级中的数据传播的方式，将至少一个控制信号的应用过滤到第二层级的至少一个组件。在一个实施例中，当取消选择第二层次级别时，控制逻辑防止数据在第二层级中被传播，而数据在第一层级中传播。在一个实施例中，第二层级可用于独立的并行测试，同时数据继续通过第一层次级传播。

10. 发明申请

WO2009073119A1 METHOD AND APPARATUS FOR DESCRIBING COMPONENTS ADAPTED FOR DYNAMICALLY MODIFYING A SCAN PATH FOR SYSTEM-ON-CHIP TESTING 审中-公开
标题翻译：用于描述用于动态修改系统在线测试的扫描路径的组件的方法和装置
公开(公告)号：WO2009073119A1
公开(公告)日：2009-06-11
申请号：PCT/US2008/013109
申请日：2008-11-25
申请人： ALCATEL-LUCENT USA INC. , CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
发明人： CHAKRABORTY, Tapan, Jyoti , CHIANG, Chen-Huan , GOYAL, Suresh , PORTOLAN, Michele , VAN TREUREN, Bradford, Gene
IPC分类号： G01R31/317 , G01R31/3185 , G06F17/50
CPC分类号： G01R31/318583 , G01R31/31704
摘要： The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system- on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system- on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.
摘要翻译：本发明提供了用于芯片级JTAG测试的新的硬件描述语言。被称为新BSDL（NSDL）的这种新的硬件描述语言使得能够描述片上系统的测试资源，从而能够以便于对系统级芯片进行测试的方式来描述片上系统，在芯片上。本发明提供了一种用于描述片上系统的自下而上的方法。本发明支持片上系统的每个组件的算法描述，并且支持片上系统的组件之间的互连的算法描述，从而能够产生整个系统的算法描述芯片或片上系统的部分。本发明支持适于动态修改片上系统（本文称为交叉设备）的扫描路径的设备，包括用于描述这种设备的方法和使用这种设备来执行片上系统的测试。

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