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1. 发明公开

EP1434347A1 Low voltage differential signaling (LVDS) driver with pre-emphasis 有权
标题翻译： LVDS-Treiber mit Vorverzerrung
公开(公告)号：EP1434347A1
公开(公告)日：2004-06-30
申请号：EP02293229.7
申请日：2002-12-23
申请人： ALCATEL
发明人： Gajdardziew Radelinow, Andrzej
IPC分类号： H03K5/24 , H04L25/02
CPC分类号： H04L25/0282 , H04L25/0276
摘要： A Low Voltage Differential Signaling [LVDS] Driver with Pre-emphasis and comprising a primary stage (MP3-MP6, MN3-MN6) having a first switching circuit (MP5, MP6, MN5, MN6) arranged to provide a sequence of pulses (OUT1; OUT2) at a predetermined current level (11), a secondary stage (MP7-MP9, MN7-MN9) having a second switching circuit (MP8, MP9, MN8, MN9) arranged to provide an additional current level (I2) for the pulses, and a control circuit arranged to provide control signals ( A, A ¯ ,B, B ¯ ) for controlling the first and second switching circuits. The control circuit is adapted to detect a difference in level between two consecutive pulses of the sequence and to provide accordingly control signals ( A, A ¯ , B , B ¯ ) to the first (MP5, MP6, MN5, MN6) and second (MP8, MP9, MN8, MN9) switching circuits. The control signals are such that when two consecutive pulses of the sequence are different, the additional current level (I2) is added to the predetermined current level (I1), whilst when two consecutive pulses of the sequence are identical, the additional current level (I2) is subtracted from the predetermined current level (I1).
摘要翻译：低压差分信号ÄLVDSÜ驱动器，其具有预加重并且包括具有第一开关电路（MP5，MP6，MN5，MN6）的初级级（MP3-MP6，MN3-MN6），其被布置成提供脉冲序列（OUT1; OUT2 ），具有布置成为脉冲提供附加电流电平（I2）的第二开关电路（MP8，MP9，MN8，MN9）的次级（MP7-MP9，MN7-MN9）以及控制电路，被布置成提供用于控制第一和第二开关电路的控制信号（A，A，B，B）。控制电路适于检测序列的两个连续脉冲之间的电平差，并相应地向第一（MP5，MP6，MN5，MN6）和第二（MP8， MP9，MN8，MN9）开关电路。控制信号使得当序列的两个连续脉冲不同时，附加电流电平（I2）被加到预定电流电平（I1），而当序列的两个连续脉冲相同时，附加电流电平 I2）从预定电流电平（I1）中减去。

2. 发明授权

EP1434347B1 Low voltage differential signaling (LVDS) driver with pre-emphasis 有权
标题翻译： LVDS驱动器与预加重
公开(公告)号：EP1434347B1
公开(公告)日：2007-02-14
申请号：EP02293229.7
申请日：2002-12-23
申请人： ALCATEL
发明人： Gajdardziew Radelinow, Andrzej
IPC分类号： H03K5/24 , H04L25/02
CPC分类号： H04L25/0282 , H04L25/0276

3. 发明公开

EP1445902A1 Low voltage differential signaling (LVDS) receiver 有权
标题翻译： Niederspannungsdifferenzsignal（LVDS） - Empfänger
公开(公告)号：EP1445902A1
公开(公告)日：2004-08-11
申请号：EP03290323.9
申请日：2003-02-10
申请人： ALCATEL
发明人： Gajdardziew Radelinow, Andrzej
IPC分类号： H04L25/02
CPC分类号： H04L25/0292 , H04L25/0272 , H04L25/0286 , H04L25/03878
摘要： The present invention is related to a device comprising, between a differential pair of inputs, a differential pre-amplifier (HPA1, HPA2), an offset-reducing block (ORB) cascaded with said differential pre-amplifier (HPA1, HPA2) and arranged for reducing the offset generated by said differential pre-amplifier, and a buffering block (BB) in series with said offset-reducing block (ORB) and arranged for amplifying and buffering the output voltage of said offset-reducing block.
摘要翻译：本发明涉及一种器件，包括差分输入之间的差分前置放大器（HPA1，HPA2），与所述差分前置放大器（HPA1，HPA2）级联的偏移减小块（ORB），并且被布置用于减少由所述差分前置放大器产生的偏移量，以及与所述偏移减小块（ORB）串联的缓冲块（BB），并被布置成用于放大和缓冲所述偏移减小块的输出电压。

4. 发明授权

EP1445902B1 Low voltage differential signaling (LVDS) receiver 有权
标题翻译：低电压差分信号（LVDS） - 接收器
公开(公告)号：EP1445902B1
公开(公告)日：2006-05-17
申请号：EP03290323.9
申请日：2003-02-10
申请人： ALCATEL
发明人： Gajdardziew Radelinow, Andrzej
IPC分类号： H04L25/02
CPC分类号： H04L25/0292 , H04L25/0272 , H04L25/0286 , H04L25/03878

5. 发明公开

EP1434348A1 Wideband common-mode regulation circuit 审中-公开
标题翻译： Breitband-Gleichtaktregler
公开(公告)号：EP1434348A1
公开(公告)日：2004-06-30
申请号：EP03290814.7
申请日：2003-03-31
申请人： ALCATEL
发明人： Gajdardziew Radelinow, Andrzej
IPC分类号： H03K5/24 , H03F3/45 , H04L25/02
CPC分类号： H04L25/0274 , H03F1/08 , H03F3/45475 , H03F3/45479 , H03F3/45928 , H03F3/45964 , H03F2200/36 , H03F2203/45418 , H03F2203/45616 , H03K5/003 , H04L25/028
摘要： A wideband common-mode regulation circuit for coupling a differential amplifier, or more particularly a Low Voltage Differential Signaling driver LVDS, to a load generally constituted by a telecommunication transmission line. The regulation circuit only comprises a first resistive pair (R1, R2) to sense the common-mode voltage at the differential input terminals (INP, INN), a second resistive pair (R3, R4) to force the voltage across the load to a predetermined value, and an active device (OTA, INV) coupled between the junction points of the first and the second resistive pairs. The active device is an Operational Transconductance Amplifier (OTA) or, preferably, an inverter (INV). Owing to reduced number of non-dominant poles in the common-mode open-loop transfer characteristic, this regulation circuit provides common-mode loop stability for wide common-mode loop bandwidth.
摘要翻译：一种宽带共模调节电路，用于将差分放大器，或更具体地，低电压差分信号驱动器LVDS耦合到通常由电信传输线构成的负载。调节电路仅包括用于感测差分输入端（INP，INN）上的共模电压的第一电阻对（R1，R2），将第二电阻对（R3，R4）强制为负载的电压以及耦合在第一和第二电阻对的连接点之间的有源器件（OTA，INV）。有源器件是操作跨导放大器（OTA）或者优选地是反相器（INV）。由于共模开环传输特性中非极性极数的减少，该调节电路为宽共模环路带宽提供共模环路稳定性。

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