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1. 发明申请

WO2023009348A1 REDUCED POWER CLOCK GENERATOR FOR LOW POWER DEVICES 审中-公开
公开(公告)号：WO2023009348A1
公开(公告)日：2023-02-02
申请号：PCT/US2022/037503
申请日：2022-07-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： GIBNEY, Thomas, J. , BRANOVER, Alexander, J. , DOCTOR, Mihir Shaileshbhai , HE, Xiaojie , PAUL, Indrani , TSIEN, Benjamin , PETRY, John, P. , KATARI, Pitchaiah
IPC分类号： G06F1/3237 , G06F1/06
摘要： A disclosed technique includes triggering entry into a clock bypass mode, in which a bypass clock generator provides clock signals to functional elements and a primary clock generator does not provide clock signals to functional elements; and triggering exit from the clock bypass mode, in which the bypass clock generator does not provide clock signals to the functional elements and the primary clock generator does provide clock signals to the functional elements.

2. 发明申请

WO2023009308A1 HIERARCHICAL STATE SAVE AND RESTORE FOR DEVICE WITH VARYING POWER STATES 审中-公开
公开(公告)号：WO2023009308A1
公开(公告)日：2023-02-02
申请号：PCT/US2022/036849
申请日：2022-07-12
申请人： ADVANCED MICRO DEVICES, INC.
发明人： PETRY, John, P. , BRANOVER, Alexander, J. , TSIEN, Benjamin , WEAVER, Christopher, T. , KOSONOCKY, Stephen, V. , PAUL, Indrani , GIBNEY, Thomas, J. , DOCTOR, Mihir, Shaileshbhai
IPC分类号： G06F3/06
摘要： A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.

3. 发明申请

WO2012074998A1 PARTITIONING OF MEMORY DEVICE FOR MULTI-CLIENT COMPUTING SYSTEM 审中-公开
标题翻译：用于多客户端计算系统的存储设备的分区
公开(公告)号：WO2012074998A1
公开(公告)日：2012-06-07
申请号：PCT/US2011/062385
申请日：2011-11-29
申请人： ADVANCED MICRO DEVICES, INC. , GIBNEY, Thomas, J. , KORAN, Patrick, J.
发明人： GIBNEY, Thomas, J. , KORAN, Patrick, J.
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1647 , G06F9/5016 , G06F12/0653 , G06F13/1626
摘要： A method, computer program product, and system are provided for accessing a memory device. For instance, the method can include partitioning one or more memory banks of the memory device into a first and a second set of memory banks. The method also can allocate a first plurality of memory cells within the first set of memory banks to a first memory operation of a first client device and a second plurality of memory cells within the second set of memory banks to a second memory operation of a second client device. This memory allocation can allow access to the first and second sets of memory banks when a first and a second memory operation are requested by the first and second client devices, respectively. Further, access to a data bus between the first client device, or the second client device, and the memory device can also be controlled based on whether the first memory address or the second memory address is accessed to execute the first or second memory operation.
摘要翻译：提供了一种访问存储器件的方法，计算机程序产品和系统。例如，该方法可以包括将存储器件的一个或多个存储体划分成第一和第二组存储器组。该方法还可以将第一组存储器组内的第一多个存储器单元分配给第二存储体组内的第一客户端设备和第二多个存储器单元的第一存储器操作到第二存储器组的第二存储器操作客户端设备。当第一和第二客户机设备请求第一和第二存储器操作时，该存储器分配可以允许访问第一和第二组存储器组。此外，还可以基于访问第一存储器地址还是第二存储器地址来执行第一或第二存储器操作来控制对第一客户端设备或第二客户端设备与存储设备之间的数据总线的访问。

4. 发明公开

EP2646925A1 PARTITIONING OF MEMORY DEVICE FOR MULTI-CLIENT COMPUTING SYSTEM 审中-公开
标题翻译：分区的存储设备对于多客户端计算机系统
公开(公告)号：EP2646925A1
公开(公告)日：2013-10-09
申请号：EP11802207.8
申请日：2011-11-29
申请人： Advanced Micro Devices, Inc.
发明人： GIBNEY, Thomas, J. , KORAN, Patrick, J.
IPC分类号： G06F13/16 , G06F12/06
CPC分类号： G06F13/1647 , G06F9/5016 , G06F12/0653 , G06F13/1626
摘要： A method, computer program product, and system are provided for accessing a memory device. For instance, the method can include partitioning one or more memory banks of the memory device into a first and a second set of memory banks. The method also can allocate a first plurality of memory cells within the first set of memory banks to a first memory operation of a first client device and a second plurality of memory cells within the second set of memory banks to a second memory operation of a second client device. This memory allocation can allow access to the first and second sets of memory banks when a first and a second memory operation are requested by the first and second client devices, respectively. Further, access to a data bus between the first client device, or the second client device, and the memory device can also be controlled based on whether the first memory address or the second memory address is accessed to execute the first or second memory operation.

5. 发明公开

EP4377766A1 REDUCED POWER CLOCK GENERATOR FOR LOW POWER DEVICES 审中-实审
公开(公告)号：EP4377766A1
公开(公告)日：2024-06-05
申请号：EP22850099.7
申请日：2022-07-18
申请人： Advanced Micro Devices, Inc.
发明人： GIBNEY, Thomas, J. , BRANOVER, Alexander, J. , DOCTOR, Mihir Shaileshbhai , HE, Xiaojie , PAUL, Indrani , TSIEN, Benjamin , PETRY, John, P. , KATARI, Pitchaiah
IPC分类号： G06F1/3237 , G06F1/06
CPC分类号： Y02D10/00 , G06F1/08 , G06F1/3237 , G06F1/324 , G06F1/3265 , G06F1/3218 , G09G5/008 , G09G2330/02120130101

6. 发明公开

EP4377783A1 HIERARCHICAL STATE SAVE AND RESTORE FOR DEVICE WITH VARYING POWER STATES 审中-实审
公开(公告)号：EP4377783A1
公开(公告)日：2024-06-05
申请号：EP22850080.7
申请日：2022-07-12
申请人： Advanced Micro Devices, Inc.
发明人： PETRY, John, P. , BRANOVER, Alexander, J. , TSIEN, Benjamin , WEAVER, Christopher, T. , KOSONOCKY, Stephen, V. , PAUL, Indrani , GIBNEY, Thomas, J. , DOCTOR, Mihir, Shaileshbhai
IPC分类号： G06F3/06
CPC分类号： Y02D10/00 , G06F9/4418 , G06F1/3287 , G06F1/3203

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