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1. 发明申请

WO1996021273A2 TWO-TRANSISTOR ZERO-POWER ELECTRICALLY-ALTERABLE NON-VOLATILE LATCH 审中-公开
标题翻译：双转子零电压可变电压非易失性锁存器
公开(公告)号：WO1996021273A2
公开(公告)日：1996-07-11
申请号：PCT/US1996000306
申请日：1996-01-04
申请人： ACTEL CORPORATION
发明人： ACTEL CORPORATION , KOWSHIK, Vikram
IPC分类号： H03K03/356
CPC分类号： H03K17/24 , H01L27/115 , H03K3/356008
摘要： A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A P-Channel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.
摘要翻译：双晶体管零功率可电可变非易失性锁存元件包括输入节点，输出节点和擦除节点。 P沟道MOS晶体管具有连接到第一电位源的源极，连接到输出节点的漏极，连接到输入节点的控制栅极和电容耦合到控制栅极的浮动栅极。 N沟道MOS晶体管具有连接到低于第一电位的第二电位源的源极，连接到输出节点的漏极，连接到输入节点的控制栅极，以及电容耦合到控制器的浮动栅极栅极并电连接到P沟道MOS晶体管的浮置栅极。 P沟道MOS晶体管和N沟道MOS晶体管的浮置栅极经由隧道电介质电容耦合到擦除节点。

2. 发明公开

EP0801844A2 TWO-TRANSISTOR ZERO-POWER ELECTRICALLY-ALTERABLE NON-VOLATILE LATCH 失效
标题翻译：双管电薇拉·桑塔德ROYAL骂人TERM触发器具有零功耗
公开(公告)号：EP0801844A2
公开(公告)日：1997-10-22
申请号：EP96907003.0
申请日：1996-01-04
申请人： ACTEL CORPORATION
发明人： KOWSHIK, Vikram
IPC分类号： H01L27 , H03K3 , H03K17 , H03K19
CPC分类号： H03K17/24 , H01L27/115 , H03K3/356008
摘要： A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A P-Channel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.

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