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1. 发明专利

KR20210032710A KR20210032710A - Thin Film Transistor Having The Oxide-Semiconductor 审中-公开
公开(公告)号：KR20210032710A
公开(公告)日：2021-03-25
申请号：KR1020190114069A
申请日：2019-09-17
申请人： 엘지디스플레이 주식회사 , 한국과학기술원
发明人： 전상훈 , 지광환 , 장기석
IPC分类号： H01L29/786
CPC分类号： H01L29/7869 , H01L21/28568 , H01L29/78606 , H01L29/78618
摘要： 본 발명은 산화물 반도체를 포함하는 박막 트랜지스터에 관한 것으로, 특히 넓은 파장대역의 빛을 감지할 수 있는 박막 트랜지스터에 관한 것이다.
이를 위하여 본 발명은, 제 1 반도체층과 제 2 반도체층을 포함하는 반도체층을 포함하며, 상기 제 1 반도체층은 산화물 반도체 물질을 포함하고, 상기 제 2 반도체층은 전이금속 칼코겐 화합물을 포함하며, 상기 제 1 반도체층과 제 2 반도체층은 접합되어 형성된 박막 트랜지스터를 제공한다.

2. 发明公开

KR1020020009125A 이종접합 바이폴라 트랜지스터의 제조방법 无效
标题翻译：用于制造异质结双极晶体管的方法
公开(公告)号：KR1020020009125A
公开(公告)日：2002-02-01
申请号：KR1020000042488
申请日：2000-07-24
申请人： 한국과학기술원 , 에이치엔에스하이텍 (주)
发明人： 전상훈 , 홍성철 , 윤태호 , 구흥섭 , 조세형
IPC分类号： H01L29/737
CPC分类号： H01L29/66318 , H01L29/7304 , H01L29/7371
摘要： PURPOSE: A method for fabricating a hetero junction bipolar transistor is provided to improve productivity by simplifying a process for fabricating a hetero junction bipolar transistor. CONSTITUTION: An emitter metal(54) is deposited on a semiconductor substrate formed with an InGaAs/GaAs layer(51), an InGaP layer(52), and a GaAs layer(53). The InGaAs/GaAs layer(51) is etched selectively by using the emitter metal(54) as a masking material. A thin film(55) including Si3N4, SiO2, and TiW is deposited on a surface of the InGaP layer(52) and a surface of the emitter metal(54). A photo-resist is patterned on the thin film(55) by using a contact alignment device and a base opening is formed thereby. The thin film(55) located on the base opening is opened by using a dry etch method or a wet etch method. The wet etch process for the InGaP layer(52) is performed. A base metal(57) is deposited thereon. A base contact is formed by lifting off the photo-resist.
摘要翻译：目的：提供一种用于制造异质结双极晶体管的方法，通过简化用于制造异质结双极晶体管的工艺来提高生产率。构成：在由InGaAs / GaAs层（51），InGaP层（52）和GaAs层（53）形成的半导体衬底上沉积发射极金属（54）。通过使用发射极金属（54）作为掩模材料，选择性地蚀刻InGaAs / GaAs层（51）。包括Si 3 N 4，SiO 2和TiW的薄膜（55）沉积在InGaP层（52）的表面和发射极金属（54）的表面上。通过使用接触对准装置在薄膜（55）上形成光致抗蚀剂，由此形成基部开口。位于基座开口上的薄膜（55）通过使用干蚀刻法或湿式蚀刻法打开。执行InGaP层（52）的湿蚀刻工艺。贱金属（57）沉积在其上。通过剥离光致抗蚀剂形成基底接触。

3. 发明授权

KR100379614B1 이종접합 바이폴라 트랜지스터 및 그 제조방법 失效
标题翻译： 이종접합바이폴라트랜지스터및그제조방법
公开(公告)号：KR100379614B1
公开(公告)日：2003-04-10
申请号：KR1020000038250
申请日：2000-07-05
申请人： 한국과학기술원
发明人： 전상훈 , 홍성철
IPC分类号： H01L29/737
摘要： PURPOSE: A heterojunction bipolar transistor and a fabricating method thereof are provided to increase a breakdown voltage between a base and a collector by forming a concave groove on a surface of a collector layer. CONSTITUTION: An N type collector layer(120) is formed on a part of a surface of a semi-insulating substrate(110) formed with GaAs. A P+ type base layer is formed on a center of a surface of the N type collector layer(120). A collector electrode(125) is formed on an edge of the collector layer(120). An emitter layer(140) and an emitter contact layer(145) are formed on a center of a base layer. A base electrode(135) is formed on an edge of the base layer(130). A concave groove(A) is formed on a surface of the collector layer(120) between the base layer(130) and the collector electrode(125). A path of current is determined by a depth of the concave groove(A). An interval between the base layer(140) and the collector electrode(125) can be increased regardless of a thickness of the collector layer(120).
摘要翻译：目的：提供异质结双极晶体管及其制造方法，以通过在集电极层的表面上形成凹槽来增加基极与集电极之间的击穿电压。构成：在形成有GaAs的半绝缘基板（110）的表面的一部分上形成N型集电极层（120）。 P +型基极层形成在N型集电极层（120）的表面的中心。集电极（125）形成在集电极层（120）的边缘上。发射极层（140）和发射极接触层（145）形成在基极层的中心。基极（135）形成在基极层（130）的边缘上。凹槽（A）形成在基极层（130）和集电极电极（125）之间的集电极层（120）的表面上。电流路径由凹槽（A）的深度决定。不管集电极层（120）的厚度如何，基极层（140）和集电极电极（125）之间的间隔都可以增加。

4. 发明公开

KR1020020004391A 이종접합 바이폴라 트랜지스터 및 그 제조방법 失效
标题翻译：异相双极晶体管及其制作方法
公开(公告)号：KR1020020004391A
公开(公告)日：2002-01-16
申请号：KR1020000038250
申请日：2000-07-05
申请人： 한국과학기술원
发明人： 전상훈 , 홍성철
IPC分类号： H01L29/737
摘要： PURPOSE: A heterojunction bipolar transistor and a fabricating method thereof are provided to increase a breakdown voltage between a base and a collector by forming a concave groove on a surface of a collector layer. CONSTITUTION: An N type collector layer(120) is formed on a part of a surface of a semi-insulating substrate(110) formed with GaAs. A P+ type base layer is formed on a center of a surface of the N type collector layer(120). A collector electrode(125) is formed on an edge of the collector layer(120). An emitter layer(140) and an emitter contact layer(145) are formed on a center of a base layer. A base electrode(135) is formed on an edge of the base layer(130). A concave groove(A) is formed on a surface of the collector layer(120) between the base layer(130) and the collector electrode(125). A path of current is determined by a depth of the concave groove(A). An interval between the base layer(140) and the collector electrode(125) can be increased regardless of a thickness of the collector layer(120).
摘要翻译：目的：提供异质结双极晶体管及其制造方法，通过在集电体层的表面上形成凹槽来提高基极与集电体之间的击穿电压。构成：在形成有GaAs的半绝缘性基板（110）的表面的一部分上形成有N型集电体层（120）。在N型集电体层（120）的表面的中央形成有P +型基层。集电极（125）形成在集电极层（120）的边缘上。发射极层（140）和发射极接触层（145）形成在基底层的中心。基底电极（135）形成在基底层（130）的边缘上。在基底层（130）和集电极（125）之间的集电体层（120）的表面上形成凹槽（A）。电流的路径由凹槽（A）的深度决定。无论集电极层（120）的厚度如何，可以增加基极层（140）和集电极（125）之间的间隔。

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