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1. 发明授权

KR100689834B1 웨이퍼 코팅장치 및 이를 이용한 웨이퍼 코팅방법 有权
标题翻译： WAFER涂料设备和使用该涂料的WAFER涂料方法
公开(公告)号：KR100689834B1
公开(公告)日：2007-03-08
申请号：KR1020050066949
申请日：2005-07-22
申请人： 삼성전자주식회사
发明人： 우상윤 , 이중현 , 한영국 , 윤광섭 , 이시형
IPC分类号： H01L21/027
摘要： 웨이퍼 코팅장치 및 웨이퍼 코팅방법을 제공한다. 상기 웨이퍼 코팅장치는 물과 같은 액체 및 상기 액체의 표면에 부유되는 자기조립단분자를 담는 액조; 및 상기 액조의 내부로 복수매의 웨이퍼들을 함침 및 인양하는 지그유니트를 구비한다. 이와 아울러, 상기 자기조립단분자막을 복수매의 웨이퍼에 코팅시키는 웨이퍼 코팅방법을 제공한다.

2. 发明公开

KR1020060134239A 광학 부재 홀더 및 이를 갖는 투영 노광 장치 有权
标题翻译：光学元件夹具和投影曝光装置
公开(公告)号：KR1020060134239A
公开(公告)日：2006-12-28
申请号：KR1020050053767
申请日：2005-06-22
申请人： 삼성전자주식회사
发明人： 심우석 , 이중현 , 한영국 , 윤광섭 , 이시형
IPC分类号： H01L21/027
CPC分类号： G02B7/00 , G03F7/701 , G03F7/70825 , H01L21/683
摘要： An optical element holder and a projection exposing apparatus having the optical element holder are provided to select one optical element corresponding to a reticle pattern among plural optical elements by revolving the optical elements on the basis of a center axis of a support element. A support element(134) supports plural optical elements(132a,132d) to be arranged in a circumference direction. The optical elements form a different type illumination light. Rotational driving units(136,142) rotate the support element and the optical elements so that the optical elements revolves on the basis of a center axis of the support element and rotates on its own center axis. The support element has a disk shaped. Plural holes where the optical elements are inserted are formed in the circumference direction. Plural accommodations(138a,138d) are respectively inserted into the holes to be rotatable and accommodate the optical elements.
摘要翻译：提供具有光学元件保持器的光学元件保持器和投影曝光装置，通过基于支撑元件的中心轴旋转光学元件来选择与多个光学元件相对应的光罩图案的一个光学元件。支撑元件（134）支撑沿圆周方向布置的多个光学元件（132a，132d）。光学元件形成不同类型的照明光。旋转驱动单元（136,142）使支撑元件和光学元件旋转，使得光学元件基于支撑元件的中心轴线旋转并且在其自身的中心轴线上旋转。支撑元件具有盘形。在圆周方向上形成插入有光学元件的多个孔。多个住宅（138a，138d）分别插入孔中以可旋转并容纳光学元件。

3. 发明授权

KR100564578B1 비직교형 반도체 메모리 소자의 자기 정렬 콘택 패드형성방법 失效
标题翻译：非垂直半导体存储器件自对准接触焊盘的成形方法
公开(公告)号：KR100564578B1
公开(公告)日：2006-03-28
申请号：KR1020030067433
申请日：2003-09-29
申请人： 삼성전자주식회사
发明人： 이은미 , 구두훈 , 이중현 , 여기성
IPC分类号： H01L21/28
CPC分类号： H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： 비직교형 반도체 메모리 소자의 자기 정렬 콘택 패드 형성방법에 대하여 개시한다. 본 발명에 따른 SAC 패드 형성방법은 대각선형 또는 분리형 활성 영역을 가지는 비직교형 반도체 소자에 적용된다. 본 발명의 일 실시예에 따르면, 먼저 대각선형 활성 영역을 가지는 반도체 기판 상에 열방향으로 신장된 다수의 게이트 라인 구조물을 형성하고, 그 결과물 상에 게이트 라인 구조물을 덮는 층간 절연막을 형성한다. 계속해서, 층간 절연막 상에 포토레지스트막을 형성한 다음, 바아 타입, 웨이브 타입 또는 리버스 액티브 타입의 패턴을 가진 포토마스크를 사용하여 노광 및 현상함으로써 포토레지스트막 패턴을 형성한다. 그리고, 포토레지스트막 패턴을 식각 마스크로 사용하여 층간 절연막을 식각함으로써 소오스/드레인 영역을 노출시키는 콘택 홀을 형성한 뒤에 콘택 홀을 도전 물질로 채움으로써 콘택 패드를 형성한다.
반도체, 메모리, 대각선형 활성 영역, 분리형 활성 영역, SAC

4. 发明公开

KR1020050031209A 레지스트 리플로우 측정 키 및 이를 이용한 반도체 소자의미세 패턴 형성 방법 失效
标题翻译：用于测量反射率的关键和形成半导体器件精细图案的方法
公开(公告)号：KR1020050031209A
公开(公告)日：2005-04-06
申请号：KR1020030067434
申请日：2003-09-29
申请人： 삼성전자주식회사
发明人： 이두열 , 여기성 , 조한구 , 이중현
IPC分类号： H01L21/027
CPC分类号： H01L22/34 , G03F7/40 , H01L21/0273
摘要： A key for measuring the reflow amount of resist and a method of forming a fine pattern of a semiconductor device are provided to improve a throughput by monitoring the flow amount of a resist pattern on a wafer within a short period of time. A first reflow key(100) is arranged around a first center point(C1) on a substrate. The first reflow key includes a plurality of first pattern elements(110-140) which are formed with patterns having different radiuses of curvature of both sides of a first center line(100c). A second reflow key(200) is arranged around a second center point(C2) on the substrate. The second reflow key includes a plurality of second pattern elements(210-240) which are formed with patterns having different radiuses of curvature of both sides of a second center line(200c).
摘要翻译：提供了用于测量抗蚀剂的回流量的键以及形成半导体器件的精细图案的方法，以通过在短时间内监视晶片上的抗蚀剂图案的流量来提高生产率。第一回流键（100）围绕基板上的第一中心点（C1）布置。第一回流键包括形成有第一中心线（100c）的两侧具有不同曲率半径的图案的多个第一图案元件（110-140）。在基板上的第二中心点（C2）周围布置有第二回流键（200）。第二回流键包括形成有第二中心线（200c）的两侧具有不同的曲率半径的图案的多个第二图案元件（210-240）。

5. 发明公开

KR1020050024668A 반도체 소자 제조를 위한 포토마스크 레이아웃 및이로부터 얻어진 포토마스크 无效
标题翻译：用于生产半导体器件的光电隔离器和用于控制易用性的光电子产品
公开(公告)号：KR1020050024668A
公开(公告)日：2005-03-11
申请号：KR1020030060747
申请日：2003-09-01
申请人： 삼성전자주식회사
发明人： 이두열 , 여기성 , 이성우 , 조한구 , 이중현
IPC分类号： H01L21/027
摘要： PURPOSE: A photomask layout used in production of a semiconductor device and a photomask created thereby are provided to improve OCV(On-Chip line width Variation) and pattern fidelity by reducing selectively a grid size. CONSTITUTION: A photomask layout includes a predetermined pattern(12) to print a predetermined shape on a semiconductor substrate. The predetermined pattern includes a plurality of segments(22,24,26). The predetermined pattern includes a first pattern region(12a) having a first OPC grid size unit and a second pattern region(12b) having a second OPC grid size unit smaller than the first OPC grid size unit. Each of the first and second pattern regions is used for forming one segment.
摘要翻译：目的：提供用于生产半导体器件的光掩模布局和由此产生的光掩模，以通过选择性地减小栅格尺寸来改善OCV（片上线宽度变化）和图案保真度。构成：光掩模布局包括在半导体衬底上印刷预定形状的预定图案（12）。预定图案包括多个段（22,24,26）。预定图案包括具有第一OPC网格尺寸单元的第一图案区域（12a）和具有小于第一OPC网格尺寸单元的第二OPC网格尺寸单元的第二图案区域（12b）。第一和第二图案区域中的每一个用于形成一个段。

6. 发明公开

KR1020020078086A 반도체 메모리 소자 및 이를 한정하기 위한 마스크 패턴 无效
标题翻译：半导体存储器件和掩模图案用于定义它们
公开(公告)号：KR1020020078086A
公开(公告)日：2002-10-18
申请号：KR1020010017947
申请日：2001-04-04
申请人： 삼성전자주식회사
发明人： 이중현 , 조한구
IPC分类号： H01L27/108
CPC分类号： H01L27/10808 , G11C5/025 , H01L27/0207
摘要： PURPOSE: A mask pattern for defining a semiconductor memory device is provided to remarkably decrease probability of a bridge, by upward or downward shifting even-numbered widthwise storage node electrodes among a plurality of storage node electrodes disposed on a semiconductor substrate by a predetermined length. CONSTITUTION: A transparent substrate(20) is prepared. A plurality of mask layers defining the type of the storage node electrode(22) are formed on the transparent substrate. An even-numbered widthwise mask layer among the plurality of mask layers is shifted upward or downward by a predetermined length.
摘要翻译：目的：提供一种用于限定半导体存储器件的掩模图案，通过将布置在半导体衬底上的多个存储节点电极中的偶数横向存储节点电极向上或向下移动预定长度来显着降低桥的概率。构成：制备透明基材（20）。在透明基板上形成限定存储节点电极（22）的类型的多个掩模层。多个掩模层中的偶数横向掩模层向上或向下移动预定长度。

7. 发明公开

KR1020010016817A 반도체 제조에 사용되는 마스크 失效
标题翻译：用于制造半导体的掩模
公开(公告)号：KR1020010016817A
公开(公告)日：2001-03-05
申请号：KR1019990031955
申请日：1999-08-04
申请人： 삼성전자주식회사
发明人： 차동호 , 박준수 , 이중현 , 김인성
IPC分类号： H01L21/027
摘要： PURPOSE: A mask used for manufacturing a semiconductor is provided to improve critical dimension(CD) difference in a chip located in an edge of a wafer wherein the CD difference is caused by flare in performing an exposure process regarding the wafer. CONSTITUTION: The first region(12) has a circuit pattern and a non-circuit pattern, and light transmits one of the patterns. The second region(14) is located in an outer portion of the first region, and has a light blocking layer for exposure blocking. The third region(16) is located between the first region and the second region. The third region includes an exposure control layer for controlling a quantity of exposure passing through the third region.
摘要翻译：目的：提供用于制造半导体的掩模，以改善位于晶片边缘的芯片的临界尺寸（CD）差异，其中在执行关于晶片的曝光过程中，CD差异是由闪光引起的。构成：第一区域（12）具有电路图案和非电路图案，并且光透射其中一个图案。第二区域（14）位于第一区域的外部，并且具有用于曝光阻挡的遮光层。第三区域（16）位于第一区域和第二区域之间。第三区域包括用于控制通过第三区域的曝光量的曝光控制层。

8. 发明公开

KR1020000051049A 포토레지스트 플로우 방법 失效
标题翻译：掩模基板的制造方法和使用掩模基板的光电转换方法
公开(公告)号：KR1020000051049A
公开(公告)日：2000-08-16
申请号：KR1019990001283
申请日：1999-01-18
申请人： 삼성전자주식회사
发明人： 서전석 , 이중현
IPC分类号： H01L21/027
摘要： PURPOSE: A fabrication method of a mask substrate and a photoresist flow method are provided to enable the formation of various pattern layouts without using different mask substrates. CONSTITUTION: A mask substrate(10) includes a chromium layer(15b) having various pattern parts with different thickness formed by several photolithography processes. A first part(B) where the mask substrate(10) is entirely exposed transmits an exposure light(55) at almost 100 percents, a second part(A) where the chromium layer(15b) is thinly formed partially transmits the exposure light(55) in inverse proportion to the thickness of the chromium layer(15b), and a third part(C) where the chromium layer(15b) is thickly formed hardly transmits the exposure light(55). Therefore, respective parts of a photoresist pattern(65) formed on a semiconductor substrate(60) are exposed in a different energy, and then flowed at a different rate in a single thermal process.
摘要翻译：目的：提供掩模基板和光致抗蚀剂流动方法的制造方法，以便能够在不使用不同的掩模基板的情况下形成各种图案布局。构成：掩模基板（10）包括通过几个光刻工艺形成的具有不同厚度的各种图案部分的铬层（15b）。掩模基板（10）完全曝光的第一部分（B）以几乎100％传递曝光光（55），其中薄层（15b）薄层形成的第二部分（A）部分透射曝光光 55）与铬层（15b）的厚度成反比，而铬层（15b）厚度形成的第三部分（C）几乎不透过曝光光（55）。因此，形成在半导体衬底（60）上的光致抗蚀剂图案（65）的各个部分以不同的能量暴露，然后在单个热处理中以不同的速率流动。

9. 发明公开

KR1020000004459A 반도체 메모리장치의 제조방법 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：KR1020000004459A
公开(公告)日：2000-01-25
申请号：KR1019980025895
申请日：1998-06-30
申请人： 삼성전자주식회사
发明人： 박준수 , 이중현
IPC分类号： H01L27/10
摘要： PURPOSE: A method for manufacturing a semiconductor memory device is provided to prevent misalignment when forming a fine pattern and a contact hole. CONSTITUTION: The method for manufacturing a semiconductor memory device comprises the steps of: forming a first interlayer insulation film(740) on a exposed area of a substrate(700) and a gate pattern; forming a first bit line contact hole(800) on a memory cell area by etching the first interlayer insulation film; forming a first bit line pad(730) by depositing a conductive materials on the first bit line contact hole; forming a second interlayer insulation film(750) on the first bit line pad and the first interlayer insulation film; forming a storage area contact hole in a memory cell area and a second bit line contact hole in a peripheral circuit area by etching a predetermined area of the first and second interlayer insulation films; forming a storage pad(770) and a second bit line pad(780) by depositing a conductive materials in the storage contact hole and the second bit line contact hole; forming a third interlayer insulation film(790) on the second interlayer insulation film, the storage pad and second bit line pad; etching the second and third interlayer insulation films so as to expose a part of the first and second bit line pads; forming a bit line on the exposed first and second bit line pads and the third interlayer insulation film; forming a fourth interlayer insulation film(840) on the third interlayer insulation film and the bit line; and forming a storage contact hole(850) by etching the fourth interlayer insulation film so that a part of the storage pad can be exposed, and forming a storage node(860) by depositing a conductive materials on the storage contact hole.
摘要翻译：目的：提供一种制造半导体存储器件的方法，以在形成精细图案和接触孔时防止未对准。构成：半导体存储器件的制造方法包括以下步骤：在衬底（700）和栅极图案的暴露区域上形成第一层间绝缘膜（740）; 通过蚀刻第一层间绝缘膜在存储单元区域上形成第一位线接触孔（800）; 通过在第一位线接触孔上沉积导电材料形成第一位线焊盘（730）; 在所述第一位线焊盘和所述第一层间绝缘膜上形成第二层间绝缘膜（750）; 通过蚀刻第一和第二层间绝缘膜的预定区域，在外围电路区域中的存储单元区域和第二位线接触孔中形成存储区接触孔; 通过在所述存储接触孔和所述第二位线接触孔中沉积导电材料来形成存储焊盘（770）和第二位线焊盘（780）在所述第二层间绝缘膜上形成第三层间绝缘膜（790），所述存储焊盘和所述第二位线焊盘; 蚀刻第二和第三层间绝缘膜以暴露第一和第二位线焊盘的一部分; 在暴露的第一和第二位线焊盘和第三层间绝缘膜上形成位线; 在所述第三层间绝缘膜和所述位线上形成第四层间绝缘膜（840）; 以及通过蚀刻所述第四层间绝缘膜形成存储接触孔（850），使得所述存储焊盘的一部分能够露出，并且通过在所述存储接触孔上沉积导电材料形成存储节点（860）。

10. 发明公开

KR1020000003724A 반사 방지 캡 및 스페이서를 구비하는 반도체장치, 이의 제조방법 및 이를 이용한 포토레지스트 패턴의 제조방법 失效
标题翻译：具有间隔物和抗反射帽的半导体器件及其方法及其使用它们制造光电子的方法
公开(公告)号：KR1020000003724A
公开(公告)日：2000-01-25
申请号：KR1019980024994
申请日：1998-06-29
申请人： 삼성전자주식회사
发明人： 김인성 , 이중현 , 조한구
IPC分类号： H01L21/027
CPC分类号： H01L21/0276 , H01L21/28044 , H01L21/28061 , H01L21/76802
摘要： PURPOSE: A semiconductor device is provided to prevent effectively reflection of light from a reflective pattern. CONSTITUTION: The semiconductor device comprises: a semiconductor substrate(100); a reflective pattern(104p, 106p) formed on the semiconductor device; an anti-reflective cap(110p) formed on the reflective pattern; and an anti-reflective spacer(130s) formed on a side wall of the reflective pattern. The anti-reflective cap(110p) functions as a interference type anti-reflective film reducing below 20% a reflection ratio by offsetting a reflection light reflected from the reflective pattern surface and a light reflected from the anti-reflective cap surface out of a light input from an upper area of the anti-reflective cap.
摘要翻译：目的：提供半导体器件以防止有效地反射来自反射图案的光。构成：半导体器件包括：半导体衬底（100）; 形成在所述半导体器件上的反射图案（104p，106p）形成在所述反射图案上的抗反射盖（110p）以及形成在反射图案的侧壁上的抗反射间隔物（130s）。抗反射盖（110p）用作通过偏移反射图案表面反射的反射光和从光反射盖表面反射的光而将反射率降低到反射率的20％以下的干涉型抗反射膜从防反射盖的上部区域输入。

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