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1. 发明专利

JP2014160667A Display device 有权
标题翻译：显示设备
公开(公告)号：JP2014160667A
公开(公告)日：2014-09-04
申请号：JP2014080974
申请日：2014-04-10
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： EGI YUJI , NISHI TAKESHI , OGINO KIYOFUMI , SASAGAWA SHINYA , KURATA MOTOMU , SUZAWA HIDEOMI
IPC分类号： H05B33/02 , G02B1/11 , G02F1/1335 , H01L51/50 , H05B33/14
CPC分类号： H01L51/5281 , C09K11/06 , C09K2211/1011 , C09K2211/1029 , C09K2211/185 , G02B1/118 , G02F1/133502 , H01J2211/442 , H01L27/3244 , H05B33/22 , Y10T428/10
摘要： PROBLEM TO BE SOLVED: To provide a display device with excellent visibility and a function of preventing reflection, capable of further preventing reflection of external light.SOLUTION: A display device includes an anti-reflection film having a plurality of convex parts on a surface of a display screen and a protective layer formed to fill space between the convex parts. The convex parts have a flat upper surface. The external light is reflected not toward the visible side but toward the adjacent convex part. The number of times of light, in the external light entering the display device, entering the anti-reflection film is increased, and the external light reflecting toward the visible side is reduced, thereby preventing the deterioration in visibility such as reflection. Moreover, since the space between the convex parts is covered with the protective layer, the entry of dust can be prevented and the physical strength of the anti-reflection film can be increased.
摘要翻译：要解决的问题：提供具有优异的可见性和防止反射的功能的显示装置，能够进一步防止外部光的反射。显示装置包括：抗反射膜，其具有在多个凸部的表面上的多个凸部形成为用于填充凸部之间的空间的显示屏和保护层。凸部具有平坦的上表面。外部光线不向可见侧反射而朝向相邻的凸部反射。在进入显示装置的外部光进入防反射膜的光的次数增加，并且朝向可见侧反射的外部光减少，从而防止诸如反射的可见性的劣化。此外，由于凸部之间的空间被保护层覆盖，所以可以防止灰尘进入，并且可以提高抗反射膜的物理强度。

2. 发明专利

JP2013211529A Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：JP2013211529A
公开(公告)日：2013-10-10
申请号：JP2013025211
申请日：2013-02-13
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： SASAGAWA SHINYA , KURATA MOTOMU
IPC分类号： H01L21/336 , H01L21/28 , H01L29/41 , H01L29/417 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To manufacture a semiconductor device which is fine and has good yield.SOLUTION: A semiconductor device manufacturing method comprises: forming a semiconductor layer, a gate insulation layer on the semiconductor layer, a gate electrode layer on the gate insulation layer and a side wall insulation layer which covers lateral walls of the gate electrode layer; forming a conductive film which is to be a source electrode layer and a drain electrode layer so as to cover the semiconductor layer, the gate insulation layer, the gate electrode layer and the side wall insulation layer; reducing a film thickness of a region which overlaps the gate electrode layer of the conductive film by chemical mechanical polishing and performing anisotropic etching to remove the conductive film which overlaps the gate electrode layer and form the source electrode layer and the drain electrode layer in a self-alignment manner.
摘要翻译：要解决的问题：制造精细且具有良好产率的半导体器件。解决方案：半导体器件制造方法包括：在半导体层上形成半导体层，栅极绝缘层，栅极绝缘层上的栅电极层以及覆盖所述栅电极层的侧壁的侧壁绝缘层; 形成作为源电极层和漏电极层的导电膜，以覆盖半导体层，栅极绝缘层，栅极电极层和侧壁绝缘层; 通过化学机械抛光减少与导电膜的栅电极层重叠的区域的膜厚度，并进行各向异性蚀刻以去除与栅电极层重叠的导电膜，并以自身形成源极电极层和漏电极层对齐方式。

3. 发明专利

JP2013149955A Semiconductor device and semiconductor device manufacturing method 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2013149955A
公开(公告)日：2013-08-01
申请号：JP2012271904
申请日：2012-12-13
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： ISOBE ATSUO , OKAZAKI YUTAKA , HANAOKA KAZUYA , SASAGAWA SHINYA , KURATA MOTOMU
IPC分类号： H01L29/786 , H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/1225 , H01L27/10879 , H01L27/1104 , H01L27/11521 , H01L27/124 , H01L27/1248 , H01L29/1033 , H01L29/24 , H01L29/41733 , H01L29/41775 , H01L29/66742 , H01L29/66969 , H01L29/78 , H01L29/7869
摘要： PROBLEM TO BE SOLVED: To provide a transistor having high electric characteristics with good yield though having a minute structure.SOLUTION: A semiconductor device manufacturing method comprises: forming on a gate insulation film, a first conductive film which overlaps an oxide semiconductor film; selectively etching the first conductive film by a resist which is subjected to exposure by an electron beam to form a gate electrode; forming a first insulation film on the gate insulation film and the gate electrode; performing removal processing on a part of the first insulation film so as not to expose the gate electrode; forming an anti-reflection film on the first insulation film; selectively etching the anti-reflection film, the first insulation film and the gate insulation film by a resist which is subjected to exposure by an electron beam; and forming a source electrode which contacts one end of the oxide semiconductor film and one end of the first insulation film, and forming a drain electrode which contacts another end of the oxide semiconductor film and another end of the first insulation film.
摘要翻译：要解决的问题：通过具有微小的结构来提供具有高电特性的晶体管，具有良好的产率。解决方案：一种半导体器件制造方法，包括：在栅极绝缘膜上形成与氧化物半导体膜重叠的第一导电膜; 通过用电子束曝光形成栅电极的抗蚀剂选择性蚀刻第一导电膜; 在栅极绝缘膜和栅电极上形成第一绝缘膜; 对所述第一绝缘膜的一部分进行去除处理，以不露出所述栅电极; 在第一绝缘膜上形成防反射膜; 通过用电子束曝光的抗蚀剂选择性地蚀刻抗反射膜，第一绝缘膜和栅极绝缘膜; 以及形成接触所述氧化物半导体膜的一端和所述第一绝缘膜的一端的源电极，以及形成接触所述氧化物半导体膜的另一端和所述第一绝缘膜的另一端的漏电极。

4. 发明专利

JP2013062529A Semiconductor element 审中-公开
标题翻译：半导体元件
公开(公告)号：JP2013062529A
公开(公告)日：2013-04-04
申请号：JP2012256360
申请日：2012-11-22
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： SUZAWA HIDEOMI , KURATA MOTOMU , MIKAMI MAYUMI
IPC分类号： H01L29/786 , H01L21/28 , H01L29/41 , H01L29/417
CPC分类号： H01L29/7869 , H01L27/108 , H01L27/1225 , H01L29/12 , H01L29/41733 , H01L29/42384 , H01L29/66969 , H01L29/78648 , H01L29/78696 , H01L2029/42388
摘要： PROBLEM TO BE SOLVED: To provide a top-gate semiconductor element having a short channel length L and capable of microfabrication and using an oxide semiconductor, and provide a manufacturing method of the semiconductor element.SOLUTION: A semiconductor element comprises: an oxide semiconductor layer on an insulation surface; a source electrode layer and a drain electrode layer on the oxide semiconductor layer; gate insulation layers on the oxide semiconductor layer, the source electrode layer and the drain electrode layer; and a gate electrode layer on the gate insulation layer. The source electrode layer and the drain electrode layer have lateral walls, respectively, and the lateral walls contact a top face of the oxide semiconductor layer.
摘要翻译：要解决的问题：提供具有短沟道长度L并能够微细加工和使用氧化物半导体的顶栅半导体元件，并提供半导体元件的制造方法。解决方案：半导体元件包括：绝缘表面上的氧化物半导体层; 氧化物半导体层上的源电极层和漏电极层; 氧化物半导体层上的栅极绝缘层，源极电极层和漏极电极层; 以及栅极绝缘层上的栅极电极层。源电极层和漏电极层分别具有侧壁，并且侧壁与氧化物半导体层的顶面接触。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2012169610A Manufacturing method for semiconductor device, and semiconductor device 有权
标题翻译：半导体器件的制造方法和半导体器件
公开(公告)号：JP2012169610A
公开(公告)日：2012-09-06
申请号：JP2012013334
申请日：2012-01-25
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： SASAGAWA SHINYA , KURATA MOTOMU
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/146 , H01L29/41 , H01L29/417 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66969 , H01L21/441 , H01L29/41733 , H01L29/7869
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with fewer defects that has achieved microfabrication, or a semiconductor device with excellent characteristics that has achieved microfabrication.SOLUTION: A manufacturing method for a semiconductor device includes the steps of: forming a semiconductor layer; forming a first conductive layer as a single layer on the semiconductor layer; forming a first resist mask using light with a wavelength of 365 nm or less on the first conductive layer; etching the first conductive layer using the first resist mask, thereby forming a second conductive layer with a concave part; forming a second resist mask by reducing the size of the first resist mask; etching the second conductive layer using the second resist mask, thereby forming a source electrode and a drain electrode each with a tapered projection part on the periphery; forming a gate insulation layer that is in contact with a part of the semiconductor layer on the source electrode and the drain electrode; and forming a gate electrode at a position on the gate insulation layer that overlaps with the semiconductor layer.
摘要翻译：要解决的问题：提供具有实现微细加工的较少缺陷的半导体器件，或者具有实现微细加工的优异特性的半导体器件。解决方案：半导体器件的制造方法包括以下步骤：形成半导体层; 在所述半导体层上形成作为单层的第一导电层; 在所述第一导电层上形成使用波长为365nm以下的光的第一抗蚀剂掩模; 使用第一抗蚀剂掩模蚀刻第一导电层，由此形成具有凹部的第二导电层; 通过减小第一抗蚀剂掩模的尺寸形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，从而在周边形成各自具有锥形突出部的源电极和漏电极; 形成与源电极和漏电极上的半导体层的一部分接触的栅极绝缘层; 以及在栅极绝缘层上与半导体层重叠的位置处形成栅电极。版权所有（C）2012，JPO＆INPIT

6. 发明专利

JP2009260295A Method of manufacturing soi substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：JP2009260295A
公开(公告)日：2009-11-05
申请号：JP2009061101
申请日：2009-03-13
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： SUZAWA HIDEOMI , SASAGAWA SHINYA , SHIMOMURA AKIHISA , MOMO JUNPEI , KURATA MOTOMU , MURAOKA TAIGA , NEI TAKAMASA
IPC分类号： H01L21/02 , H01L21/20 , H01L21/265 , H01L21/322 , H01L27/12
CPC分类号： H01L21/76254
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SOI substrate having a single crystal semiconductor layer which can be practically utilized even if a substrate having a low heat resistant temperature such as a glass substrate is used. SOLUTION: The method includes steps for: forming an insulating film on a surface of a single crystal semiconductor substrate; applying an ion beam to the single crystal semiconductor substrate through the insulating film to form an embrittlement region in the single crystal semiconductor substrate; forming a junction layer on the insulating film; laminating a support substrate face to face with the single crystal semiconductor substrate by the junction layer; carrying out heat treatment to divide the single crystal semiconductor substrate along the embrittlement region, thereby separating the support substrate to which the single crystal semiconductor layer is attached and a part of the single crystal semiconductor substrate; carrying out first dry-etching treatment for the embrittlement region where the single crystal semiconductor layer remains; carrying out second dry-etching treatment for the surface of the single crystal semiconductor layer where the first etching treatment has been carried out; and applying a laser beam to the single crystal semiconductor layer. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造具有单晶半导体层的SOI衬底的方法，即使使用诸如玻璃衬底的耐热温度低的衬底也可以实际使用。解决方案：该方法包括以下步骤：在单晶半导体衬底的表面上形成绝缘膜; 通过绝缘膜将离子束施加到单晶半导体衬底，以在单晶半导体衬底中形成脆化区; 在绝缘膜上形成接合层; 通过接合层将支撑衬底与单晶半导体衬底面对; 进行热处理以沿着脆化区域分割单晶半导体衬底，从而分离附着有单晶半导体层的支撑衬底和单晶半导体衬底的一部分; 对残留单晶半导体层的脆化区域进行第一次干蚀刻处理; 对进行了第一蚀刻处理的单晶半导体层的表面进行第二干法蚀刻处理; 以及将激光束施加到单晶半导体层。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2014209592A 半導体装置、及び半導体装置の作製方法审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：JP2014209592A
公开(公告)日：2014-11-06
申请号：JP2014054781
申请日：2014-03-18
申请人：株式会社半導体エネルギー研究所 , Semiconductor Energy Lab Co Ltd
发明人： SASAGAWA SHINYA , KURATA MOTOMU , MURAOKA TAIGA
IPC分类号： H01L29/786 , G02F1/1368 , H01L21/336 , H01L29/41 , H01L29/417
CPC分类号： H01L29/7869 , H01L21/02521 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L29/41733 , H01L29/78696
摘要：【課題】微細化に適した半導体装置を提供する。【解決手段】絶縁表面上に島状の半導体層と、半導体層上に接して設けられ、半導体層上で離間する第1の電極及び第2の電極と、半導体層上にゲート電極と、半導体層とゲート電極の間にゲート絶縁層と、を備える。また第1の電極は及び第2の電極は、第1の導電層及び第2の導電層を有する、また島状の半導体層上において、第2の導電層は、第1の導電層の間に位置し、且つ、第2の導電層の側面の一部が第1の導電層の側面の一部と接する。さらに第2の導電層は第1の導電層よりも薄く、且つ、第2の導電層の上面が第1の導電層の上面よりも低く位置する。【選択図】図1
摘要翻译：要解决的问题：提供适用于微细加工的半导体器件。解决方案：半导体器件包括：绝缘表面上的岛状半导体层; 第一电极和第二电极，其与半导体层接触并且在半导体层上彼此相隔一定距离; 半导体层上的栅电极; 以及在半导体层和栅电极之间的栅极绝缘层。第一电极和第二电极分别具有第一导电层和第二导电层。在岛状半导体层上，第二导电层位于第一导电层之间，并且每个第二导电层的侧面的一部分接触每个第一导电层的侧面的一部分。此外，每个第二导电层比每个第一导电层薄，并且每个第二导电层的顶面位于比每个第一导电层的顶面低的位置。

8. 发明专利

JP2014199921A 半導体装置およびその作製方法有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014199921A
公开(公告)日：2014-10-23
申请号：JP2014043410
申请日：2014-03-06
申请人：株式会社半導体エネルギー研究所 , Semiconductor Energy Lab Co Ltd
发明人： SASAGAWA SHINYA , KURATA MOTOMU
IPC分类号： H01L29/786 , H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8242 , H01L21/8247 , H01L27/06 , H01L27/088 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/417 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/1259 , H01L27/1288 , H01L29/41733 , H01L29/45 , H01L29/66969 , H01L29/78696
摘要：【課題】高い電気特性を有する微細なトランジスタを歩留まりよく提供する。また、該トランジスタを含む半導体装置においても、高性能化、高信頼性化、および高生産化を達成する。【解決手段】酸化物半導体膜を微細加工する際に、ハードマスクを用いることで酸化物半導体膜の側面の凹凸を抑制することができる。具体的には、絶縁表面102上の酸化物半導体膜104と、酸化物半導体膜上の第1のハードマスク106aおよび第2のハードマスク106bと、酸化物半導体膜および第1のハードマスク上のソース電極110aと、酸化物半導体膜および第2のハードマスク上のドレイン電極110bと、ソース電極およびドレイン電極上のゲート絶縁膜112と、ゲート絶縁膜と酸化物半導体膜と重畳するゲート電極114と、を有し、第1のハードマスクおよび第2のハードマスクは、導電性を有する膜である。【選択図】図1
摘要翻译：要解决的问题：即使在包括晶体管的半导体器件中也可以提供具有高电特性，良好产率的高精度晶体管，并提高性能，可靠性和生产率。解决方案：在氧化物半导体膜的微细加工中，可以通过使用硬掩模来抑制氧化物半导体膜的侧面。具体来说，半导体器件包括：设置在绝缘表面102上的氧化物半导体膜104; 设置在氧化物半导体膜上的第一硬掩模106a和第二硬掩模106b; 设置在氧化物半导体膜和第一硬掩模上的源电极110a; 设置在氧化物半导体膜和第二硬掩模上的漏电极110b; 设置在源电极和漏电极上的栅极绝缘膜112; 以及与栅极绝缘膜和氧化物半导体膜重叠的栅电极114。第一个硬掩模和第二个硬掩模是具有导电性的膜。

9. 发明专利

JP2014007393A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2014007393A
公开(公告)日：2014-01-16
申请号：JP2013112752
申请日：2013-05-29
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： HONDO SUGURU , SHIMOMURA AKIHISA , FURUYAMA MASAKI , KURATA MOTOMU , HANAOKA KAZUYA , NAGAMATSU SHO , NEI TAKAMASA , HASEGAWA TORU
IPC分类号： H01L21/336 , G02F1/1368 , H01L21/28 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/788 , H01L29/792 , H01L51/50
CPC分类号： H01L29/66969 , H01L21/46 , H01L29/78618 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： PROBLEM TO BE SOLVED: To provide a transistor using an oxide semiconductor film having stable electric characteristics; and provide the transistor using the oxide semiconductor film having high on-state characteristics.SOLUTION: In a semiconductor device manufacturing method, a low-resistance oxide semiconductor film is formed and a channel region of the oxide semiconductor film is made to have high-resistance. Practically, the low-resistance oxide semiconductor film is formed by performing on the oxide semiconductor film, processing of making the oxide semiconductor film have low resistance. The processing of making the oxide semiconductor film have low resistance may be performed, for example, by a laser beam treatment or a heating treatment at not less than 450°C and not more than 740°C. Further, processing of making the channel region of the low-resistance oxide semiconductor film have high resistance may be performed, for example, plasma oxidation or oxygen ion implantation.
摘要翻译：要解决的问题：提供一种使用具有稳定电特性的氧化物半导体膜的晶体管; 并且使用具有高导通状态特性的氧化物半导体膜提供晶体管。解决方案：在半导体器件制造方法中，形成低电阻氧化物半导体膜，并且使氧化物半导体膜的沟道区域具有高电阻。实际上，通过在氧化物半导体膜上进行氧化物半导体膜的制造，具有低电阻的处理，形成低电阻氧化物半导体膜。可以例如通过在450℃以上且740℃以下的激光束处理或加热处理来进行制造氧化物半导体膜的低电阻的处理。此外，可以执行例如等离子体氧化或氧离子注入来制造低电阻氧化物半导体膜的沟道区域的高电阻的处理。

10. 发明专利

JP2013179283A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013179283A
公开(公告)日：2013-09-09
申请号：JP2013016312
申请日：2013-01-31
申请人： Semiconductor Energy Lab Co Ltd , 株式会社半導体エネルギー研究所
发明人： SASAGAWA SHINYA , KURATA MOTOMU
IPC分类号： H01L21/336 , H01L21/28 , H01L21/8242 , H01L21/8244 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/11 , H01L27/115 , H01L29/417 , H01L29/786 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To apply a stable electric characteristic and achieve high reliability in a semiconductor device having a transistor including an oxide semiconductor film and provide a configuration which achieves high-speed response and high-speed drive of the semiconductor device.SOLUTION: In a semiconductor device having a transistor in which an oxide semiconductor film, a gate insulation film, and a gate electrode layer are laminated in this order, and in which a side wall insulation layer including a first side wall insulation layer, a second side wall insulation layer and a third side wall insulation layer is provided on a side surface of the gate electrode layer, the first side wall insulation layer is brought into contact with a part of an upper surface of the gate insulation film and the side surface of the gate electrode layer, the second side wall insulation layer including an insulation film including a metal element with lower oxygen permeability than the first side wall insulation layer is brought into contact with a part of an upper surface of the oxide semiconductor film, a side surface of the gate insulation film and a side surface of the first side wall insulation layer, and the third side wall insulation layer is brought into contact with a side surface of the second side wall insulation layer.
摘要翻译：要解决的问题：在具有包括氧化物半导体膜的晶体管的半导体器件中应用稳定的电特性并实现高可靠性，并且提供实现半导体器件的高速响应和高速驱动的配置。解决方案：在具有其中氧化物半导体膜，栅极绝缘膜和栅极电极层依次层叠的晶体管的半导体器件，并且其中侧壁绝缘层包括第一侧壁绝缘层，第二侧壁绝缘层层和第三侧壁绝缘层设置在栅电极层的侧表面上，第一侧壁绝缘层与栅极绝缘膜的上表面的一部分和栅电极的侧表面接触层，所述第二侧壁绝缘层包括绝缘膜，所述绝缘膜包括具有比所述第一侧低的氧透过率的金属元素使绝缘层与氧化物半导体膜的上表面的一部分，栅极绝缘膜的侧面和第一侧壁绝缘层的侧面和第三侧壁绝缘层接触，与第二侧壁绝缘层的侧表面接触。

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