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1. 发明授权

US06507899B1 Interface for a memory unit 有权
标题翻译：存储单元的接口
公开(公告)号：US06507899B1
公开(公告)日：2003-01-14
申请号：US09460534
申请日：1999-12-13
申请人： Klaus Oberlaender , Sabeen Randhawa , Yannick Martelloni , Manfred Henftling , Rami Zemach , Zohar Peleg , Christian Wiedholz , Gigy Baror , Doron Shoham , Oded Trainin , Niv Margalit
发明人： Klaus Oberlaender , Sabeen Randhawa , Yannick Martelloni , Manfred Henftling , Rami Zemach , Zohar Peleg , Christian Wiedholz , Gigy Baror , Doron Shoham , Oded Trainin , Niv Margalit
IPC分类号： G06F1208
CPC分类号： G06F12/0215
摘要： An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.
摘要翻译：描述了一种用于将数据处理单元与具有控制输入，地址信号输入，数据信号输入和数据信号输出的存储单元耦合的接口电路。接口电路包括具有输入和输出的地址缓冲器，所述输入接收来自所述数据处理单元的地址信号，第一多路复用器将所述存储单元与所述地址缓冲器的所述输出或所述地址信号相耦合，数据具有输入和输出的缓冲器，所述输入接收来自所述数据处理单元的数据信号，并且所述输出与所述存储器数据输入耦合;第二多路复用器，用于选择所述存储器数据信号输出或所述数据缓冲器输出;以及比较器用于将所述地址信号与来自所述地址缓冲器输出的信号进行比较，产生控制所述第二多路复用器的控制信号。

2. 发明授权

US5218314A High resolution, multi-frequency digital phase-locked loop 失效
标题翻译：高分辨率，多频数字锁相环
公开(公告)号：US5218314A
公开(公告)日：1993-06-08
申请号：US890691
申请日：1992-05-29
申请人： Avner Efendovich , Afek Yachin , Amos Intrater , Zohar Peleg , Coby Sella , Zeev Bikowsky
发明人： Avner Efendovich , Afek Yachin , Amos Intrater , Zohar Peleg , Coby Sella , Zeev Bikowsky
IPC分类号： H03L7/00
CPC分类号： H03L7/00
摘要： The present invention provides a phase-locked loop in which an internal oscillator is fed into a high resolution tapped delay line. One output of the tapped delay line is selected by selection logic to generate the output clock. The output clock is phase compared with the input signal, which is either a clock signal or a NRZ data signal, and in any case, is a signal with frequency that is a division by two of the frequency of the internal oscillator and the source of which is also the internal oscillator. Then a decision is made, according to the phase detection, whether to select the next output of the delay line, the previous one, or remain with the current one. Therefore, if a change in the frequency is needed, then if an integer multiple or division of the original frequency is selected for the internal oscillator, synchronization will be unchanged, and furthermore, both the output clock and the input signal will simultaneously switch to the new frequency. All this is done by additional logic that enables actual switching to the new frequency only after an entire cycle of the low frequency has ended.
摘要翻译：本发明提供一种锁相环，其中将内部振荡器馈入高分辨率抽头延迟线。抽头延迟线的一个输出由选择逻辑选择以产生输出时钟。输出时钟与输入信号进行相位比较，输入信号是时钟信号或NRZ数据信号，在任何情况下都是频率为内部振荡器的频率除以2的信号，这也是内部振荡器。然后，根据相位检测，决定是选择延迟线的下一个输出，前一个还是与当前延迟线保持一致。因此，如果需要频率变化，则如果为内部振荡器选择原始频率的整数倍或除法，同步将不变，此外，输出时钟和输入信号都将同时切换到新频率所有这些都是通过额外的逻辑完成的，只有在低频的整个周期结束后才能实际切换到新频率。

3. 发明申请

US20070104228A1 Asymmetric Differential Timing 审中-公开
标题翻译：不对称差分时序
公开(公告)号：US20070104228A1
公开(公告)日：2007-05-10
申请号：US11555283
申请日：2006-11-01
申请人： Ron Cohen , Bar Gal-On , Zohar Peleg , David Brief
发明人： Ron Cohen , Bar Gal-On , Zohar Peleg , David Brief
IPC分类号： H04J3/06
CPC分类号： H04J3/0691
摘要： A system and method for reconstructing a service clock between two, first and second subsystems communicating therebetween, comprising a first subsystem operative to generate first subsystem timestamps, a second subsystem operative to generate second subsystem timestamps at a second frequency different from the first timestamps, wherein the generations of both first and second timestamps are based on sampling of the service clock by a common clock available at both subsystems, and an aligner for arithmetically aligning the different first and second subsystem timestamps to reconstruct the service clock.
摘要翻译：一种用于重建在其间通信的两个第一和第二子系统之间的服务时钟的系统和方法，包括：第一子系统，用于产生第一子系统时间戳;第二子系统，用于以不同于所述第一时间戳的第二频率生成第二子系统时间戳，其中第一和第二时间戳的代都基于通过在两个子系统可用的公共时钟的服务时钟的采样，以及用于对不同的第一和第二子系统时间戳进行算术对准以重构服务时钟的对准器。

4. 发明授权

US5250940A Multi-mode home terminal system that utilizes a single embedded general purpose/DSP processor and a single random access memory 失效
标题翻译：使用单个嵌入式通用/ DSP处理器和单个随机存取存储器的多模式家庭终端系统
公开(公告)号：US5250940A
公开(公告)日：1993-10-05
申请号：US642928
申请日：1991-01-18
申请人： Maurice Valentaten , Bernd Moeschen , Yehezkel Friedman , Yom-Tov Sidi , Zeev Bikowsky , Zohar Peleg
发明人： Maurice Valentaten , Bernd Moeschen , Yehezkel Friedman , Yom-Tov Sidi , Zeev Bikowsky , Zohar Peleg
IPC分类号： G06F15/78 , G06F3/14 , G09G5/395 , H04N7/14 , H04N7/173 , G09G1/02
CPC分类号： H04N7/148 , G06F3/14
摘要： A multi-mode home terminal system utilizes a single embedded processor and a single RAM for performing modem operations, graphics/video processing and general purpose control tasks. The multi-mode home terminal system supports a wide range of video/graphics standards, modems and voice algorithms. Home terminal input data to be displayed on an associated monitor can be decoded to any display list format or directly to the system's frame buffer. The display lists, frame buffer, font area, and embedded processor memory are located in the same single random access memory, thus allowing the use of a single RAM for DSP data, display lists, video buffers, voice compression/decompression algorithms and embedded controller tasks. The system is flexible for programming the desired video standard, modem type and display list format. Since both the video function and the embedded processor are supported by the same RAM, a RAM arbiter resolves bus contention.

5. 发明申请

US20090092861A1 INTEGRATED FUEL CELL CONTROLLER FOR DEVICES 审中-公开
标题翻译：集成式燃料电池控制器
公开(公告)号：US20090092861A1
公开(公告)日：2009-04-09
申请号：US12238180
申请日：2008-09-25
申请人： Zeev Aleyraz , Zohar Peleg , Gennadi Finkelshtain
发明人： Zeev Aleyraz , Zohar Peleg , Gennadi Finkelshtain
IPC分类号： H01M8/02 , H01M8/00
CPC分类号： H02J7/34 , H01M8/04037 , H01M8/04365 , H01M8/04559 , H01M8/04589 , H01M8/04619 , H01M8/04731 , H01M8/0488 , H01M8/04888 , H01M8/0491 , H01M8/04917 , H01M16/006 , H02J2001/004
摘要： Power unit for an electronic device and process for control and regulation of an electronic device powered by a fuel cell. Power unit includes a fuel cell having a low output voltage between 0.3 and 1V, and a conversion device coupled to the fuel cell to convert an input voltage as low as 0.3 V to a higher output voltage to operate the electronic device.
摘要翻译：用于电子设备的动力单元和用于控制和调节由燃料电池供电的电子设备的过程。功率单元包括具有0.3和1V之间的低输出电压的燃料电池和耦合到燃料电池的转换装置，以将低至0.3V的输入电压转换为较高的输出电压以操作电子装置。

6. 发明授权

US07446501B2 Integrated fuel cell controller for devices 失效
标题翻译：用于设备的集成燃料电池控制器
公开(公告)号：US07446501B2
公开(公告)日：2008-11-04
申请号：US10803900
申请日：2004-03-19
申请人： Zeev Aleyraz , Zohar Peleg , Gennadi Finkelshtain
发明人： Zeev Aleyraz , Zohar Peleg , Gennadi Finkelshtain
IPC分类号： H01M10/44
CPC分类号： H02J7/34 , H01M8/04037 , H01M8/04365 , H01M8/04559 , H01M8/04589 , H01M8/04619 , H01M8/04731 , H01M8/0488 , H01M8/04888 , H01M8/0491 , H01M8/04917 , H01M16/006 , H02J2001/004
摘要： Power unit for an electronic device and process for control and regulation of an electronic device powered by a fuel cell. Power unit includes a fuel cell having a low output voltage between 0.3 and 1 V, and a conversion device coupled to the fuel cell to convert an input voltage as low as 0.3 V to a higher output voltage to operate the electronic device.
摘要翻译：用于电子设备的动力单元和用于控制和调节由燃料电池供电的电子设备的过程。功率单元包括具有0.3至1V之间的低输出电压的燃料电池和耦合到燃料电池的转换装置，以将低至0.3V的输入电压转换为较高的输出电压以操作电子设备。

7. 发明申请

US20060187822A1 Method and apparatus for partitioning allocation and management of jitter buffer memory for tdm circuit emulation applications 审中-公开
标题翻译：用于tdm电路仿真应用的抖动缓冲存储器分配和管理的方法和装置
公开(公告)号：US20060187822A1
公开(公告)日：2006-08-24
申请号：US10549678
申请日：2004-06-29
申请人： Zohar Peleg
发明人： Zohar Peleg
IPC分类号： H04L12/26 , H04L12/56 , H04L12/28
CPC分类号： H04L47/2416 , H04J3/0632 , H04J3/1611 , H04L47/10 , H04L47/22 , H04L47/27 , H04L47/283 , H04L47/30 , H04L47/32 , H04L47/34 , H04L49/90 , H04L49/901 , H04L49/9094 , H04Q2213/13292 , H04Q2213/13296
摘要： A method for partitioning allocation and management of a jitter buffer memory for TDM circuit emulation applications comprises the steps of obtaining a channel hierarchy for a plurality of packet carrying channels having different channel rates, obtaining a packet sequential number, and using the channel hierarchy and the packet sequential number, generating a base-address in the jitter buffer memory. Each channel is allocated a space in the buffer memory that is proportional to its rate, and out-of-order packets are automatically reordered by the jitter buffer.
摘要翻译：用于分配用于TDM电路仿真应用的抖动缓冲存储器的分配和管理的方法包括以下步骤：获得具有不同信道速率的多个分组承载信道的信道层级，获得分组序列号，以及使用信道分级和分组顺序号，在抖动缓冲存储器中生成基地址。每个通道在缓冲存储器中分配一个与其速率成比例的空间，并且乱序缓冲区自动重新排序乱序数据包。

8. 发明申请

US20050206342A1 Integrated fuel cell controller for devices 失效
标题翻译：用于设备的集成燃料电池控制器
公开(公告)号：US20050206342A1
公开(公告)日：2005-09-22
申请号：US10803900
申请日：2004-03-19
申请人： Zeev Aleyraz , Zohar Peleg , Gennadi Finkelshtain
发明人： Zeev Aleyraz , Zohar Peleg , Gennadi Finkelshtain
IPC分类号： H01M8/04 , H01M10/44 , H01M16/00 , H02J7/34
CPC分类号： H02J7/34 , H01M8/04037 , H01M8/04365 , H01M8/04559 , H01M8/04589 , H01M8/04619 , H01M8/04731 , H01M8/0488 , H01M8/04888 , H01M8/0491 , H01M8/04917 , H01M16/006 , H02J2001/004
摘要： Power unit for an electronic device and process for control and regulation of an electronic device powered by a fuel cell. Power unit includes a fuel cell having a low output voltage between 0.3 and 1 V, and a conversion device coupled to the fuel cell to convert an input voltage as low as 0.3 V to a higher output voltage to operate the electronic device.
摘要翻译：用于电子设备的动力单元和用于控制和调节由燃料电池供电的电子设备的过程。功率单元包括具有0.3至1V之间的低输出电压的燃料电池和耦合到燃料电池的转换装置，以将低至0.3V的输入电压转换为较高的输出电压以操作电子设备。

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