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1. 发明授权

US07842578B2 Method for fabricating MOS devices with a salicided gate and source/drain combined with a non-silicide source drain regions 有权
标题翻译：用于制造具有阴极栅极和与非硅化物源极漏极区域结合的源极/漏极的MOS器件的方法
公开(公告)号：US07842578B2
公开(公告)日：2010-11-30
申请号：US11615967
申请日：2006-12-23
申请人： Zhong Shan Hong , Xian Yong Pu
发明人： Zhong Shan Hong , Xian Yong Pu
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L21/823835 , H01L27/14612 , H01L27/14689 , H01L29/665
摘要： A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.
摘要翻译：一种用于制造集成电路器件的方法，例如CMOS图像传感器。该方法包括提供具有第一器件区域和第二器件区域的半导体衬底。该方法形成覆盖第一和第二器件区域的栅极多晶硅层。该方法形成覆盖栅极多晶硅层的硅化物层。该方法图案化硅化物层和栅极多晶硅层，以在第一器件区域中形成第一硅化栅结构，在第二器件区域形成第二硅化栅结构。该方法还包括形成覆盖第二器件区域的阻挡层。该方法形成了覆盖第一源区和与第一硅化栅结构相关联的第一漏区的硅化物材料，并且使用阻挡层保持与第二硅化物栅结构相关联的第二源极区和与第二硅化物栅结构无关的第二漏区。

2. 发明申请

US20080145990A1 METHOD AND STRUCTURE FOR FABRICATING MOS DEVICES WITH A SALICIDED GATE AND SOURCE/DRAIN COMBINED WITH A NON-SILICIDE SOURCE DRAIN REGIONS 有权
标题翻译：用非水硅源排水区组合的卤化物门和源/排出物制造MOS器件的方法和结构
公开(公告)号：US20080145990A1
公开(公告)日：2008-06-19
申请号：US11615967
申请日：2006-12-23
申请人： Zhong Shan Hong , Xian Yong Pu
发明人： Zhong Shan Hong , Xian Yong Pu
IPC分类号： H01L21/336
CPC分类号： H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L21/823835 , H01L27/14612 , H01L27/14689 , H01L29/665
摘要： A method for fabricating an integrated circuit device, e.g., CMOS image sensor. The method includes providing a semiconductor substrate, which has a first device region and a second device region. The method forms a gate polysilicon layer overlying the first and second device regions. The method forms a silicide layer overlying the gate polysilicon layer. The method patterns the silicide layer and gate polysilicon layer to form a first silicided gate structure in the first device region and a second silicided gate structure in the second device region. The method also includes forming a blocking layer overlying the second device region. The method forms a silicide material overlying a first source region and a first drain region associated with the first silicided gate structure, and maintaining a second source region and a second drain region associated with the second silicided gate structure free from any silicide using the blocking layer.
摘要翻译：一种用于制造集成电路器件的方法，例如CMOS图像传感器。该方法包括提供具有第一器件区域和第二器件区域的半导体衬底。该方法形成覆盖第一和第二器件区域的栅极多晶硅层。该方法形成覆盖栅极多晶硅层的硅化物层。该方法图案化硅化物层和栅极多晶硅层，以在第一器件区域中形成第一硅化栅结构，在第二器件区域形成第二硅化栅结构。该方法还包括形成覆盖第二器件区域的阻挡层。该方法形成了覆盖第一源区和与第一硅化栅结构相关联的第一漏区的硅化物材料，并且使用阻挡层保持与第二硅化物栅结构相关联的第二源极区和与第二硅化物栅结构无关的第二漏区。

3. 发明申请

US20110089479A1 SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE 有权
标题翻译：可控闪存EEPROM存储单元，带有浮动栅极间隔器，由控制门和制造方法
公开(公告)号：US20110089479A1
公开(公告)日：2011-04-21
申请号：US12887496
申请日：2010-09-21
申请人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
发明人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
IPC分类号： H01L29/788 , H01L21/283
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328
摘要： A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.
摘要翻译：作为闪存器件的浮动栅极的多晶硅间隔物。这种间隔结构的优点是减小单元尺寸，这对于最先进的闪速存储器技术是期望的。在优选实施例中，浮动栅极可以自对准到电池选择晶体管的选择栅极的附近和/或附近。在优选实施例中，本发明在去除之后使用干蚀刻保留了在选择晶体管栅极的漏极侧上的多晶硅间隔物结构的隧道氧化物层。更优选地，本方法提供一定量的隧道氧化物以保留，以防止存储单元的漏极区域中的活性硅区域被干蚀刻气体蚀刻。

4. 发明申请

US20120146123A1 SCALABLE FLASH EEPROM MEMORY CELL WITH FLOATING GATE SPACER WRAPPED BY CONTROL GATE AND METHOD OF MANUFACTURE 审中-公开
标题翻译：可控闪存EEPROM存储单元，带有浮动栅极间隔器，由控制门和制造方法
公开(公告)号：US20120146123A1
公开(公告)日：2012-06-14
申请号：US13361937
申请日：2012-01-30
申请人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
发明人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L27/11521 , H01L29/40114 , H01L29/42328
摘要： A flash memory cell includes a substrate having a surface region and a flash memory cell structure on the surface region. The flash memory cell structure includes a gate dielectric layer on the surface region, a select gate on the gate dielectric layer, a cap oxide layer on the select gate, an oxide spacer on a first edge of the select gate, a tunnel oxide layer on a first region and on a second region of the surface region. The second region is an active region. The flash memory cell structure further includes a poly spacer on the first edge of the oxide spacer and a portion of the tunnel oxide layer on the first region, an ONO layer on at least the poly spacer and a control gate layer on the ONO layer.
摘要翻译：闪存单元包括在表面区域上具有表面区域和闪存单元结构的基板。闪存单元结构包括表面区域上的栅极介电层，栅极电介质层上的选择栅极，选择栅极上的覆盖氧化物层，选择栅极的第一边缘上的氧化物隔离层，第一区域和表面区域的第二区域。第二个地区是一个活跃的地区。闪存单元结构还包括在氧化物隔离物的第一边缘上的多隔离物和第一区域上的隧道氧化物层的一部分，至少在多隔离物上的ONO层和ONO层上的控制栅极层。

5. 发明授权

US08119479B2 Scalable flash EEPROM memory cell with floating gate spacer wrapped by control gate and method of manufacture 有权
标题翻译：具有浮动栅极隔离器的可扩展闪存EEPROM存储单元，由控制门和制造方法包裹
公开(公告)号：US08119479B2
公开(公告)日：2012-02-21
申请号：US12887496
申请日：2010-09-21
申请人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
发明人： Jin Da , Yun Yang , Wei Lu , Zhong Shan Hong , Zuo Ya Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11521 , H01L29/42328
摘要： A polysilicon spacer as a floating gate of a Flash memory device. An advantage of such spacer structure is to reduce a cell size, which is desirable for state-of-the-art Flash memory technology. In a preferred embodiment, the floating gate can be self-aligned to a nearby and/or within a vicinity of the select gate of the cell select transistor. In a preferred embodiment, the present invention preserves a tunnel oxide layer after the removal, using dry etching, a polysilicon spacer structure on the drain side of the select transistor gate. More preferably, the present method provides for a certain amount of tunnel oxide to remain so as to prevent the active silicon area in the drain region of the memory cell from being etched by the dry etching gas.
摘要翻译：作为闪存器件的浮动栅极的多晶硅间隔物。这种间隔结构的优点是减小单元尺寸，这对于最先进的闪速存储器技术是期望的。在优选实施例中，浮动栅极可以自对准到电池选择晶体管的选择栅极的附近和/或附近。在优选实施例中，本发明在去除之后使用干蚀刻保留了在选择晶体管栅极的漏极侧上的多晶硅间隔物结构的隧道氧化物层。更优选地，本方法提供一定量的隧道氧化物以保留，以防止存储单元的漏极区域中的活性硅区域被干蚀刻气体蚀刻。

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